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Texas Instruments TMS320C6745 DSP - Page 73

Texas Instruments TMS320C6745 DSP
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TMS320C674x Megamodule
73
SPRUH91DMarch 2013Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
DSP Subsystem
Table 2-1. DSP Interrupt Map (continued)
Event Interrupt Name Source
117 UMC_ED2 C674x-UMC
118 PDC_INT C674x-PDC
119 SYS_CMPA C674x-SYS
120 PMC_CMPA C674x-PMC
121 PMC_CMPA C674x-PMC
122 DMC_CMPA C674x-DMC
123 DMC_CMPA C674x-DMC
124 UMC_CMPA C674x-UMC
125 UMC_CMPA C674x-UMC
126 EMC_CMPA C674x-EMC
127 EMC_BUSERR C674x-EMC
2.2.2.1.1 Interrupt Controller Registers
For more information on the DSP interrupt controller (INTC) registers, see the TMS320C674x DSP
Megamodule Reference Guide (SPRUFK5).
2.2.2.1.2 NMI Interrupt
In addition to the interrupts listed in Table 2-1, the DSP also supports a special interrupt that behaves
more like an exception, non-maskable interrupt (NMI). The NMI interrupt is controlled by two registers in
the System Configuration Module, the chip signal register (CHIPSIG) and the chip signal clear register
(CHIPSIG_CLR).
The NMI interrupt is asserted by writing a 1 to the CHIPSIG4 bit in CHIPSIG. The NMI interrupt is cleared
by writing a 1 to the CHIPSIG4 bit in CHIPSIG_CLR. For more information on the System Configuration
Module, CHIPSIG, and CHIPSIG_CLR, see the System Configuration (SYSCFG) Module chapter.
2.2.2.2 Power-Down Controller (PDC)
The C674x megamodule includes a power-down controller (PDC). The PDC can power-down all of the
following components of the C674x megamodule and internal memories of the DSP subsystem:
C674x CPU
Level 1 program memory controller (PMC)
Level 1 data memory controller (DMC)
Level 2 unified memory controller (UMC)
Extended memory controller (EMC)
Internal Direct Memory Access controller (IDMA)
L1P memory
L1D memory
L2 memory
This device supports the static power-down feature from the C674x megamodule. The TMS320C674x
DSP Megamodule Reference Guide (SPRUFK5) describes the power-down control in more detail.
Static power-down: The PDC initiates power-down (clock gating) of the entire C674x megamodule and
all internal memories immediately upon command from software.

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