Texas Instruments TMS320C6745 DSP - Queue Manager Linking RAM Region 0 Size Register (LRAM0 SIZE); Queue Manager Linking RAM Region 1 Base Address Register (LRAM1 BASE); Queue Manager Linking RAM Region 0 Size Register (LRAM0 SIZE) Field Descriptions; Queue Manager Linking RAM Region 1 Base Address Register (LRAM1 BASE) Field Descriptions

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SPRUH91D–March 2013–Revised September 2016
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31.4.82 Queue Manager Linking RAM Region 0 Size Register (LRAM0SIZE)
The queue manager linking RAM region 0 size register (LRAM0SIZE) sets the size of the array of linking
pointers that are located in Region 0 of Linking RAM. The size specified the number of descriptors for
which linking information is stored in this region. It does not support byte accesses. The queue manager
linking RAM region 0 size register (LRAM0SIZE) is shown in Figure 31-108 and described in Table 31-
112.
Figure 31-108. Queue Manager Linking RAM Region 0 Size Register (LRAM0SIZE)
31 16
Reserved
R-0
15 14 13 0
Reserved REGION0_SIZE
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 31-112. Queue Manager Linking RAM Region 0 Size Register (LRAM0SIZE)
Field Descriptions
Bit Field Value Description
31-14 Reserved 0 Reserved
13-0 REGION0_SIZE 0-3FFFh This field indicates the number of entries that are contained in the linking RAM region 0. A
descriptor with index less than region0_size value has its linking location in region 0. A
descriptor with index greater than region0_size has its linking location in region 1. The queue
manager will add the index (left shifted by 2 bits) to the appropriate regionX_base_addr to get
the absolute 32-bit address to the linking location for a descriptor.
31.4.83 Queue Manager Linking RAM Region 1 Base Address Register (LRAM1BASE)
The queue manager linking RAM region 1 base address register (LRAM1BASE) is used to set the base
address for the first portion of the Linking RAM. This address must be 32-bit aligned. It is used by the
Queue Manager to calculate the 32-bit linking address for a given descriptor index. It does not support
byte accesses. The queue manager linking RAM region 1 base address register (LRAM1BASE) is shown
in Figure 31-109 and described in Table 31-113.
Figure 31-109. Queue Manager Linking RAM Region 1 Base Address Register (LRAM1BASE)
31 0
REGION1_BASE
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 31-113. Queue Manager Linking RAM Region 1 Base Address Register (LRAM1BASE)
Field Descriptions
Bit Field Value Description
31-0 REGION1_BASE 0-FFFF FFFFh This field stores the base address for the second region of the linking RAM. This may be
anywhere in 32-bit address space but would be typically located in off-chip memory.