Texas Instruments TMS320C6745 DSP - EMIFA Pins Specific to SDRAM; EMIFA Pins Specific to Asynchronous Memory

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SPRUH91D–March 2013–Revised September 2016
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External Memory Interface A (EMIFA)
Table 18-2. EMIFA Pins Specific to SDRAM
Pin(s) I/O Description
EMA_CS[0] O Active-low chip enable pin for SDRAM devices.
This pin is connected to the chip-select pin of the attached SDRAM device and is used for
enabling/disabling commands. By default, the EMIFA keeps this SDRAM chip select active, even
if the EMIFA is not interfaced with an SDRAM device. This pin is deactivated when accessing the
asynchronous memory bank and is reactivated on completion of the asynchronous assess.
EMA_RAS O Active-low row address strobe pin.
This pin is connected to the RAS pin of the attached SDRAM device and is used for sending
commands to the device.
EMA_CAS O Active-low column address strobe pin.
This pin is connected to the CAS pin of the attached SDRAM device and is used for sending
commands to the device.
EMA_SDCKE O Clock enable pin.
This pin is connected to the CKE pin of the attached SDRAM device and is used for issuing the
SELF REFRESH command which places the device in self refresh mode. See Section 18.2.4.7
for details.
EMA_CLK O SDRAM clock pin.
This pin is connected to the CLK pin of the attached SDRAM device. See Section 18.2.1 for
details on the clock signal.
Table 18-3. EMIFA Pins Specific to Asynchronous Memory
Pin(s) I/O Description
EMA_CS[5:2] O Active-low chip enable pins for asynchronous devices.
These pins are meant to be connected to the chip-select pins of the attached asynchronous
device. These pins are active only during accesses to the asynchronous memory.
EMA_WAIT I Wait input with programmable polarity / NAND Flash ready input.
Not all devices support both EMA_WAIT[1] and EMA_WAIT[0], see your device-specific data
manual to determine support on each device.
A connected asynchronous device can extend the strobe period of an access cycle by asserting
the EMA_WAIT input to the EMIFA as described in Section 18.2.5.7. To enable this functionality,
the EW bit in the asynchronous n configuration register (CEnCFG) must be set to 1. The WP0
and WP1 bits in the asynchronous wait cycle configuration register (AWCC) must be configured to
define the polarity of the EMA_WAIT pin. The CSn_WAIT bit in AWCC must also be configured to
determine which EMA_WAIT[n] signal is used for memory accesses.
When the CS2NAND/CS3NAND/CS4NAND/CS5NAND bit in the NAND Flash control register
(NANDFCR) is set, this pin instead functions as a NAND Flash ready input.
EMA_OE O Active-low pin enable for asynchronous devices.
This pin provides a signal which is active-low during the strobe period of an asynchronous read
access cycle.
EMA_A_RW O EMIFA asynchronous read/write control.
This pin stays high during reads and stays low during writes (same duration as CS).