Registers
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SPRUH91D–March 2013–Revised September 2016
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Enhanced Direct Memory Access (EDMA3) Controller
16.4.2.6.4 Interrupt Pending Register (IPR)
If the TCINTEN and/or ITCINTEN bit in the channel option parameter (OPT) is set to 1 in the PaRAM
entry associated with the channel (DMA or QDMA), then the EDMA3TC (for normal completion) or the
EDMA3CC (for early completion) returns a completion code on transfer or intermediate transfer
completion. The value of the returned completion code is equal to the TCC bit in OPT for the PaRAM
entry associated with the channel.
When an interrupt transfer completion code with TCC = n is detected by the EDMA3CC, then the
corresponding bit is set in the interrupt pending register (IPR.In, if n = 0 to 31). Note that once a bit is set
in the interrupt pending registers, it remains set; it is your responsibility to clear these bits. The bits set in
IPR are cleared by writing a 1 to the corresponding bits in the interrupt clear registers (ICR).
The IPR is shown in Figure 16-73 and described in Table 16-52.
Figure 16-73. Interrupt Pending Register (IPR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
I31 I30 I29 I28 I27 I26 I25 I24 I23 I22 I21 I20 I19 I18 I17 I16
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 16-52. Interrupt Pending Register (IPR) Field Descriptions
Bit Field Value Description
31-0 In Interrupt pending for TCC = 0-31.
0 Interrupt transfer completion code is not detected or was cleared.
1 Interrupt transfer completion code is detected (In = 1, n = EDMA3TC[5:0]).
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