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Registers
683
SPRUH91D–March 2013–Revised September 2016
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EMAC/MDIO Module
17.3.3.46 Transmit Channel DMA Head Descriptor Pointer Registers (TX0HDP-TX7HDP)
The transmit channel 0-7 DMA head descriptor pointer register (TXnHDP) is shown in Figure 17-84 and
described in Table 17-83.
Figure 17-84. Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP)
31 0
TXnHDP
R/W-x
LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset
Table 17-83. Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP)
Field Descriptions
Bit Field Value Description
31-0 TXnHDP 0-FFFF FFFFh Transmit channel n DMA Head Descriptor pointer. Writing a transmit DMA buffer descriptor
address to a head pointer location initiates transmit DMA operations in the queue for the
selected channel. Writing to these locations when they are nonzero is an error (except at reset).
Host software must initialize these locations to 0 on reset.
17.3.3.47 Receive Channel DMA Head Descriptor Pointer Registers (RX0HDP-RX7HDP)
The receive channel 0-7 DMA head descriptor pointer register (RXnHDP) is shown in Figure 17-85 and
described in Table 17-84.
Figure 17-85. Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP)
31 0
RXnHDP
R/W-x
LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset
Table 17-84. Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP)
Field Descriptions
Bit Field Value Description
31-0 RXnHDP 0-FFFF FFFFh Receive channel n DMA Head Descriptor pointer. Writing a receive DMA buffer descriptor
address to this location allows receive DMA operations in the selected channel when a channel
frame is received. Writing to these locations when they are nonzero is an error (except at reset).
Host software must initialize these locations to 0 on reset.
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