www.ti.com
Registers
539
SPRUH91D–March 2013–Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Enhanced Direct Memory Access (EDMA3) Controller
16.4.2.6.5 Interrupt Clear Register (ICR)
The bits in the interrupt pending register (IPR) are cleared by writing a 1 to the corresponding bits in the
interrupt clear register (ICR); writes of 0 have no effect. All set bits in IPR must be cleared to allow
EDMA3CC to assert additional transfer completion interrupts.
The ICR is shown in Figure 16-74 and described in Table 16-53.
Figure 16-74. Interrupt Clear Register (ICR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
I31 I30 I29 I28 I27 I26 I25 I24 I23 I22 I21 I20 I19 I18 I17 I16
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
LEGEND: W = Write only; -n = value after reset
Table 16-53. Interrupt Clear Register (ICR) Field Descriptions
Bit Field Value Description
31-0 In Interrupt clear register for TCC = 0-31.
0 No effect.
1 Corresponding bit in the interrupt pending register (IPR) is cleared (In = 0).
To Next Page