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Texas Instruments TMS320C6745 DSP - Peripheral Bus Burst Priority Register (BPRIO); Peripheral Bus Burst Priority Register (BPRIO) Field Descriptions

Texas Instruments TMS320C6745 DSP
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SPRUH91D–March 2013–Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
External Memory Interface B (EMIFB)
19.4.5 Peripheral Bus Burst Priority Register (BPRIO)
The peripheral bus burst priority register (BPRIO) helps prevent command starvation within the SDRAM
memory controller. To avoid command starvation, the SDRAM memory controller momentarily raises the
priority of the oldest command in the command FIFO after a set number of 32-bit transfers have been
made on the external memory bus. The PRIO_RAISE bit sets the number of transfers that must be made
before the SDRAM memory controller raises the priority of the oldest command. The BPRIO is shown in
Figure 19-19 and described in Table 19-30.
Proper configuration of the BPRIO is critical to correct system operation. The EMIFB controller always
prioritizes accesses to open rows as highest if there is any bank conflict regardless of master priority. This
is done to allow most efficient utilization of the SDRAM. However, it could lead to excessive blocking of
high priority masters. If the PRIO_RAISE bits are cleared to 00h, then the EMIFB controller always honors
the master priority, regardless of open row/bank status. For most systems, the BPRIO should be set to a
moderately low value to provide an acceptable balance of SDRAM efficiency and latency for high priority
masters (for example, 10h or 20h).
Figure 19-19. Peripheral Bus Burst Priority Register (BPRIO)
31 16
Reserved
R-0
15 8 7 0
Reserved PRIO_RAISE
R-0 R/W-FFh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-30. Peripheral Bus Burst Priority Register (BPRIO) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 All writes to these bit(s) must always have a value of 0.
7-0 PRIO_RAISE 0-FFh Priority raise old counter. Specifies the number of 32-bit memory transfers after which the SDRAM
memory controller will elevate the priority of the oldest command in the command FIFO. Clearing to
00h will ensure master priority is strictly honored (at the cost of decreased EMIFB efficiency, as
open row will always be closed immediately if any bank conflict occurs). Recommended setting for
typical system operation is between 10h and 20h.

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