Texas Instruments TMS320C6745 DSP - Receive High-Frequency Clock Control Register (AHCLKRCTL); Receive High-Frequency Clock Control Register (AHCLKRCTL) Field Descriptions

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SPRUH91D–March 2013–Revised September 2016
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Multichannel Audio Serial Port (McASP)
24.1.18 Receive High-Frequency Clock Control Register (AHCLKRCTL)
The receive high-frequency clock control register (AHCLKRCTL) configures the receive high-frequency
master clock (AHCLKR) and the receive clock generator. The AHCLKRCTL is shown in Figure 24-51 and
described in Table 24-26.
Figure 24-51. Receive High-Frequency Clock Control Register (AHCLKRCTL)
31 16
Reserved
(A)
R-0
15 14 13 12 11 0
HCLKRM HCLKRP Reserved
(A)
HCLKRDIV
R/W-1 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
A If writing to this field, always write the default value for future device compatibility.
Table 24-26. Receive High-Frequency Clock Control Register (AHCLKRCTL) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Reserved. The reserved bit location always returns the default value. A value written to this field
has no effect. If writing to this field, always write the default value for future device compatibility.
15 HCLKRM Receive high-frequency clock source bit.
0 External receive high-frequency clock source from AHCLKR pin.
1 Internal receive high-frequency clock source from output of programmable high clock divider.
14 HCLKRP Receive bitstream high-frequency clock polarity select bit.
0 Not inverted. AHCLKR is not inverted before programmable bit clock divider. In the special case
where the receive bit clock (ACLKR) is internally generated and the programmable bit clock divider
is set to divide-by-1 (CLKRDIV = 0 in ACLKRCTL), AHCLKR is directly passed through to the
ACLKR pin.
1 Inverted. AHCLKR is inverted before programmable bit clock divider. In the special case where the
receive bit clock (ACLKR) is internally generated and the programmable bit clock divider is set to
divide-by-1 (CLKRDIV = 0 in ACLKRCTL), AHCLKR is directly passed through to the ACLKR pin.
13-12 Reserved 0 Reserved. The reserved bit location always returns the default value. A value written to this field
has no effect. If writing to this field, always write the default value for future device compatibility.
11-0 HCLKRDIV 0-FFFh Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to
AHCLKR.
0 Divide-by-1
1h Divide-by-2
2h-FFFh Divide-by-3 to divide-by-4096