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SPRUH91D–March 2013–Revised September 2016
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Enhanced Direct Memory Access (EDMA3) Controller
16.2.11 EDMA3 Transfer Controller (EDMA3TC)
The EDMA3 channel controller is the user-interface of the EDMA3 and the EDMA3 transfer controller
(EDMA3TC) is the data movement engine of the EDMA3. The EDMA3CC submits transfer requests (TR)
to the EDMA3TC and the EDMA3TC performs the data transfers dictated by the TR.
16.2.11.1 Architecture Details
16.2.11.1.1 EDMA3TC Configuration
Each transfer controller on a device is designed differently based on considerations like performance
requirements, system topology (main SCR bus width, external memory bus width), gate count, etc. The
parameters that determine the TC configurations are:
• FIFOSIZE: Determines the size in bytes for the Data FIFO that is the temporary buffer for the in-flight
data. The data FIFO is where the read return data read by the TC read controller from the source
endpoint is stored and subsequently written out to the destination endpoint by the TC write controller.
• Default Burst Size (DBS): The DBS is the maximum number of bytes per read/write command issued
by a transfer controller.
• BUSWIDTH: The width of the read and write data buses in bytes, for the TC read and write controller,
respectively. This is typically equal to the bus width of the main SCR interface.
• DSTREGDEPTH: This determines the number of Destination FIFO register set. The number of
Destination FIFO register set for a transfer controller, determines the maximum number of outstanding
transfer requests (TR pipelining).
Of the four parameters, the FIFOSIZE, BUSWIDTH, and DSTREGDEPTH values are fixed in design for a
given device. The default burst size (DBS) for each transfer controller is configurable by the chip
configuration 0 register (CFGCHIP0) in the System Configuration Module.
The burst size for each transfer controlled can be programmed to be 16-, 32-, or 64-bytes. The default
values for DBS are typically chosen for optimal performance in most intended-use conditions; therefore, if
you decide to use a value other then the default, you should evaluate the impact on performance.
Depending on the FIFOSIZE and source/destination locations the performance for the transfer can vary
significantly for different burst size values.
NOTE: It is expected that the DBS value for a transfer controller is static and should be based on
the application requirement. It is not recommended that the DBS value be changed on-the-
fly.
16.2.11.1.2 Command Fragmentation
The TC read and write controllers in conjunction with the source and destination register sets are
responsible for issuing optimally-sized reads and writes to the slave endpoints. The transfer controller
read/write transaction as specified by the transfer request packet is internally broken down into smaller
bursts; this determines the default burst size (DBS) for the transfer controller. See Section 16.2.11.1.1 for
the DBS value of each EDMA3TC.
The EDMA3TC attempts to issue the largest possible command size as limited by the DBS value or the
ACNT/BCNT value of the TR. EDMA3TC obeys the following rules:
• The read/write controllers always issue commands less than or equal to the DBS value.
• The first command of a 1D transfer is always issued so that subsequent commands align to the DBS
value.
Example 16-4 shows the command fragmentation for a DBS of 32 bytes. In summary, if the ACNT value is
larger than the DBS value, then the EDMA3TC breaks the ACNT array into DBS-sized commands to the
source/destination addresses. Each BCNT number of arrays are then serviced in succession.
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