Texas Instruments TMS320C6745 DSP - SDRAM Refresh Control Register (SDRFC); SDRAM Refresh Control Register (SDRFC) Field Descriptions

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SPRUH91D–March 2013–Revised September 2016
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External Memory Interface B (EMIFB)
19.4.2 SDRAM Refresh Control Register (SDRFC)
The SDRAM refresh control register (SDRFC) is used to configure the rate at which connected SDRAM
devices will be automatically refreshed by the EMIFB. In addition, this register is used to put the attached
SDRAM device into Self-Refresh/ Power-Down mode. The SDRFC is shown in Figure 19-15 and
described in Table 19-26.
Figure 19-15. SDRAM Refresh Control Register (SDRFC)
31 30 29 24 23 22 16
LP_MODE MCLKSTOP_EN Reserved SR_PD Reserved
R/W-0 R/W-0 R-0 R/W-0 R-0
15 0
REFRESH_RATE
R/W-04E2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-26. SDRAM Refresh Control Register (SDRFC) Field Descriptions
Bit Field Value Description
31 LP_MODE Low Power mode (Self Refresh). Writing a 1 to this bit will cause connected SDRAM devices to
be place into self-refresh mode and the EMIFB to enter the self-refresh state.
0 SDRAM is not to be placed in self-refresh/power-down mode.
1 SDRAM placed in self-refresh/power-down mode depending on the value of SR_PD bit.
30 MCLKSTOP_EN mclk Stop Enable. Writing a 1 to this bit enables mclk stopping.
0 mclk stopping disabled.
1 mclk stopping enabled.
29-24 Reserved 0 Reserved.
23 SR_PD Self-refresh or power-down select. This bit is ignored when LP_MODE bit is cleared to 0.
0 When LP_MODE = 1, clear this bit to 0 to cause connected SDRAM devices to be placed into
self-refresh mode.
1 When LP_MODE = 1, set this bit to 1 to cause connected SDRAM devices to be placed into
power-down mode.
22-16 Reserved 0 Reserved.
15-0 REFRESH_RATE 0-FFFFh Refresh Rate. Defines the rate at which connected SDRAM devices will be refreshed.
SDRAM refresh rate = EMIF rate/REFRESH_RATE
where EMIF rate is equal to EMIFB SDRAM clock rate.
Writing a value < 0100h to this field causes it to be loaded with 2 × T_RFC value from SDRAM
timing 1 register (SDTIM1).
The required refresh rate is derived from the SDRAM device data sheet.