Texas Instruments TMS320C6745 DSP - Power Domain 0 Status Register (PDSTAT0); Power Domain 0 Status Register (PDSTAT0) Field Descriptions

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SPRUH91D–March 2013–Revised September 2016
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Power and Sleep Controller (PSC)
8.6.11 Power Domain 0 Status Register (PDSTAT0)
The power domain 0 status register (PDSTAT0) is shown in Figure 8-11 and described in Table 8-16.
Figure 8-11. Power Domain 0 Status Register (PDSTAT0)
31 16
Reserved
R-0
15 12 11 10 9 8 7 5 4 0
Reserved EMUIHB Rsvd PORDONE POR Reserved STATE
R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 8-16. Power Domain 0 Status Register (PDSTAT0) Field Descriptions
Bit Field Value Description
31-12 Reserved 0 Reserved
11 EMUIHB Emulation alters domain state.
0 Interrupt is not active. No emulation altering user-desired power domain states.
1 Interrupt is active. Emulation alters user-desired power domain state.
10 Reserved 0 Reserved
9 PORDONE Power_On_Reset (POR) Done status
0 Power domain POR is not done.
1 Power domain POR is done.
8 POR Power Domain Power_On_Reset (POR) status. This bit reflects the POR status for this power
domain including all modules in the domain.
0 Power domain POR is asserted.
1 Power domain POR is de-asserted.
7-5 Reserved 0 Reserved
4-0 STATE 0-1Fh Power Domain Status.
0 Power domain is in the off state.
1h Power domain is in the on state.
2h-Fh Reserved
10h-1Ah Power domain is in transition.
1Bh-1Fh Reserved