Texas Instruments TMS320C6745 DSP - SDRAM Timing Register (SDTIMR); SDTIMR Field Calculations for the EMIFA to K4 S641632 H-TC(L)70 Interface

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SPRUH91D–March 2013–Revised September 2016
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External Memory Interface A (EMIFA)
18.3.2.1.2 SDRAM Timing Register (SDTIMR) Settings for the EMIFA to K4S641632H-TC(L)70 Interface
The fields of the SDRAM timing register (SDTIMR) should be programmed first as described in
Table 18-27 to satisfy the required timing parameters for the K4S641632H-TC(L)70. Based on these
calculations, a value of 6111 4610h should be written to SDTIMR. Figure 18-19 shows a graphical
description of how SDTIMR should be programmed.
(1)
The Samsung datasheet does not specify a t
RFC
value. Instead, Samsung specifies t
RC
as the minimum auto refresh period.
(2)
The Samsung datasheet does not specify a t
WR
value. Instead, Samsung specifies t
RDL
as last data in to row precharge minimum
delay.
Table 18-27. SDTIMR Field Calculations for the EMIFA to K4S641632H-TC(L)70 Interface
Field Name Formula
Value from K4S641632H-TC(L)70
Datasheet
Value Calculated for
Field
T_RFC T_RFC >= (t
RFC
× f
EMA_CLK
) - 1 t
RC
= 68 ns (min)
(1)
6
T_RP T_RP >= (t
RP
× f
EMA_CLK
) - 1 t
RP
= 20 ns (min) 1
T_RCD T_RCD >= (t
RCD
× f
EMA_CLK
) - 1 t
RCD
= 20 ns (min) 1
T_WR T_WR >= (t
WR
× f
EMA_CLK
) - 1 t
RDL
= 2 CLK = 20 ns (min)
(2)
1
T_RAS T_RAS >= (t
RAS
× f
EMA_CLK
) - 1 t
RAS
= 49 ns (min) 4
T_RC T_RC >= (t
RC
× f
EMA_CLK
) - 1 t
RC
= 68 ns (min) 6
T_RRD T_RRD >= (t
RRD
× f
EMA_CLK
) - 1 t
RRD
= 14 ns (min) 1
Figure 18-19. SDRAM Timing Register (SDTIMR)
31 27 26 24 23 22 20 19 18 16
0 0110 001 0 001 0 001
T_RFC T_RP Rsvd T_RCD Rsvd T_WR
15 12 11 8 7 6 4 3 0
0100 0110 0 001 0000
T_RAS T_RC Rsvd T_RRD Reserved