Introduction
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SPRUH91D–March 2013–Revised September 2016
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System Memory
4.1 Introduction
This device has multiple on-chip/off-chip memories and several external device interfaces associated with
the DSP and various subsystems. To help simplify software development, a unified memory-map is used
wherever possible to maintain a consistent view of device resources across all masters (CPU and master
peripherals).
For details on the memory addresses, actual memory supported and accessibility by various bus masters,
see the detailed memory-map information in the device-specific data manual.
4.2 DSP Memories
The DSP internal memories are accessible by the DSP and other master peripherals (as dictated by the
connectivity matrix) via the system interconnect through the DSP SDMA port. The accesses by the DSP to
its internal memory are internal to the DSP subsystem and do not go out on the system interconnect.
The DSP internal memory consists of L1P, L1D, and L2. The DSP internal memory configuration is:
• L1P memory includes 32 kB of RAM. The DSP program memory controller (PMC) allows you to
configure part or all of the L1P RAM as normal program RAM or as cache. You can configure cache
sizes of 0 kB, 4 kB, 8 kB, 16 kB, or 32 kB of the 32 kB of RAM. The default configuration is 32 kB
cache.
• L1D memory includes 32 kB of RAM. The DSP data memory controller (DMC) allows you to configure
part of the L1D RAM as normal data RAM or as cache. You can configure cache sizes of 0 kB, 4 kB, 8
kB, 16 kB, or 32 kB of the 32 kB of RAM. The default configuration is 32 kB cache.
• L2 memory includes 256 kB of RAM. The DSP unified memory controller (UMC) allows you to
configure part or all of the L2 RAM as normal RAM or as cache. You can configure cache sizes of
0 kB, 4 kB, 8 kB, 16 kB, 32 kB, 64 kB, 128 kB, or 256 kB of the 256 kB of RAM. The default
configuration is 256 kB normal RAM.
• L2 memory also includes 1024 kB of ROM.
Shared RAM
This device also offers an on-chip 128-kB shared RAM, apart from the DSP level 1 and level 2 internal
memories. This shared RAM is accessible by the DSP and also is accessible by several master
peripherals. The 128-kB shared RAM is not supported on the C6745 DSP.
External Memories
This device has two external memory interfaces that provide multiple external memory options accessible
by the CPU and master peripherals:
• EMIFA:
– 8/16-bit wide (package dependent) asynchronous EMIF module that supports asynchronous
devices such as ASRAM, NAND Flash, and NOR Flash (up to 4 devices)
– 8/16-bit wide (package dependent) NAND Flash with 4-bit ECC (up to 4 devices)
– 16-bit SDRAM with 128-MB address space (package dependent)
• EMIFB: 32/16-bit SDRAM (package dependent) with up to 256-MB SDRAM address space
Internal Peripherals
The following peripherals are internal to the DSP subsystem and are only accessible to the DSP:
• DSP interrupt controller (INTC)
• DSP power down controller (PDC)
• Bandwidth manager (BWM)
• Internal DMA (IDMA)
For more information on these internal peripherals, see the TMS320C674x DSP Megamodule Reference
Guide (SPRUFK5).
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