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SPRUH91D–March 2013–Revised September 2016
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Enhanced Direct Memory Access (EDMA3) Controller
Additionally, with each shadow region, there is an associated shadow region completion interrupt
(EDMA3CC_INTn where n denotes the shadow region number). For multi-core/hetero-core devices, the
various shadow region interrupts might be tied to the interrupt controllers for different cores. For single
core devices, all shadow region interrupts would be routed to the device interrupt controller. See your
device-specific data manual for the shadow region interrupt hookup to the device interrupt controller(s).
The DRAE associated with each shadow region acts as a secondary interrupt enable (along with the
interrupt enable register) for the respective shadow region interrupts. See Section 16.2.9 for more
information on interrupts.
Example 16-1. Resource Pool Division Across Two Regions
This example illustrates a resource pool division across two regions, assuming region 0 must be allocated 16
DMA channels (0-15) and 1 QDMA channel (0), and 16 TCC codes (0-15). Region 1 needs to be allocated 16
DMA channels (16-31) and 7 QDMA channels (1-7), and 16 TCC codes (16-31). DRAE should be equal to the
OR of the bits that are required for the DMA channels and the TCC codes:
Region 0: DRAE = 0x0000FFFF QRAE = 0x00000001 Region 1: DRAE = 0xFFFF0000 QRAE = 0x000000FE
16.2.8 Chaining EDMA3 Channels
The channel chaining capability for the EDMA3 allows the completion of an EDMA3 channel transfer to
trigger another EDMA3 channel transfer. The purpose is to allow you the ability to chain several events
through one event occurrence.
Chaining is different from linking (Section 16.2.3.7). The EDMA3 link feature reloads the current channel
parameter set with the linked parameter set. The EDMA3 chaining feature does not modify or update any
channel parameter set; it provides a synchronization event to the chained channel (see Section 16.2.4.1.3
for chain-triggered transfer requests).
Chaining is achieved at either final transfer completion or intermediate transfer completion, or both, of the
current channel. Consider a channel m (DMA/QDMA) required to chain to channel n. Channel number n
(0-31) needs to be programmed into the TCC field of channel m channel options parameter (OPT) set.
• If final transfer completion chaining (TCCHEN = 1 and ITCCHEN = 0 in channel m OPT) is enabled,
the chain-triggered event occurs after the last transfer request of channel m is submitted (early
completion) or completed (normal completion).
• If intermediate transfer completion chaining (TCCHEN = 0 and ITCCHEN = 0 in channel m OPT) is
enabled, the chain-triggered event occurs after every intermediate transfer request of channel m is
submitted (early completion) or completed (normal completion).
• If both final and intermediate transfer completion chaining (TCCHEN = 1 and ITCCHEN = 1 in channel
m OPT) are enabled, the chain-trigger event occurs after every transfer request of channel m is
submitted (early completion) or completed (normal completion).
Table 16-7 shows the number of chain event triggers occurring in different synchronized scenarios.
Consider channel 31 programmed with ACNT = 3, BCNT = 4, CCNT = 5, and TCC = 30.
Table 16-7. Chain Event Triggers
(Number of chained event triggers on channel 30)
Options A-Synchronized AB-Synchronized
TCCHEN = 1, ITCCHEN = 0 1 (Last TR) 1 (Last TR)
TCCHEN = 0, ITCCHEN = 1 19 (All but the last TR) 4 (All but the last TR)
TCCHEN = 1, ITCCHEN = 1 20 (All TRs) 5 (All TRs)
16.2.9 EDMA3 Interrupts
The EDMA3 interrupts are divided into 2 categories:
• Transfer completion interrupts
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