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SPRUH91D–March 2013–Revised September 2016
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Enhanced Direct Memory Access (EDMA3) Controller
You can enable interrupt generation at either final transfer completion or intermediate transfer completion,
or both. Consider channel m as an example.
• If the final transfer interrupt (TCINTEN = 1 and ITCINTEN = 0 in OPT) is enabled, the interrupt occurs
after the last transfer request of channel m is either submitted or completed (depending on early or
normal completion).
• If the intermediate transfer interrupt (TCINTEN = 0 and ITCINTEN = 1 in OPT) is enabled, the interrupt
occurs after every intermediate transfer request of channel m is either submitted or completed
(depending on early or normal completion).
• If both final and intermediate transfer completion interrupts (TCINTEN = 1 and ITCINTEN = 1 in OPT)
are enabled, the interrupt occurs after every transfer request of channel m is submitted or completed
(depending on early or normal completion).
Table 16-9 shows the number of interrupts occurring in different synchronized scenarios. Consider
channel 31 programmed with ACNT = 3, BCNT = 4, CCNT = 5, and TCC = 30.
Table 16-9. Number of Interrupts
Options A-Synchronized AB-Synchronized
TCINTEN = 1, ITCINTEN = 0 1 (Last TR) 1 (Last TR)
TCINTEN = 0, ITCINTEN = 1 19 (All but the last TR) 4 (All but the last TR)
TCINTEN = 1, ITCINTEN = 1 20 (All TRs) 5 (All TRs)
16.2.9.1.1 Enabling Transfer Completion Interrupts
For the EDMA3 channel controller to assert a transfer completion to the external world, the interrupts have
to be enabled in the EDMA3CC. This is in addition to setting up the TCINTEN and ITCINTEN bits in OPT
of the associated PaRAM set.
The EDMA3 channel controller has interrupt enable registers (IER) and each bit location in IER serves as
a primary enable for the corresponding interrupt pending register (IPR).
All the interrupt registers (IER, IESR, IECR, and IPR) are either manipulated from the global DMA channel
region or by way of the DMA channel shadow regions. The shadow regions provide a view to the same
set of physical registers that are in the global region.
The EDMA3 channel controller has a hierarchical completion interrupt scheme that makes use of a single
set of interrupt pending register (IPR) and single set of interrupt enable registers (IER). A second level of
interrupt masking is provided by the programmable DMA region access enable registers (DRAE). See
Figure 16-12.
For the EDMA3CC to generate the transfer completion interrupts that are associated with each shadow
region, the following conditions must be true:
• EDMA3CC_INT0: (IPR.E0 & IER.E0 & DRAE0.E0) | (IPR.E1 & IER.E1 & DRAE0.E1) | …| (IPR.En &
IER.En & DRAE0.En)
• EDMA3CC_INT1: (IPR.E0 & IER.E0 & DRAE1.E0) | (IPR.E1 & IER.E1 & DRAE1.E1) | …| (IPR.En &
IER.En & DRAE1.En)
where n is the number of shadow regions supported in the EDMA3CC for a specific device.
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