Texas Instruments TMS320C6745 DSP - 10.4 Interrupt Support; 10.4.1 Interrupt Events and Requests; 10.4.2 Interrupt Multiplexing; 10.4.3 Host-DSP Communication Interrupts

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SPRUH91D–March 2013–Revised September 2016
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System Configuration (SYSCFG) Module
(1)
The default priority settings might not be optimal for all applications. The master priority should be changed from default based
on application specific requirement, in order to get optimal performance and prioritization for masters moving data that is real
time sensitive.
(2)
The priority for EDMA3TC0 and EDMA3TC1 is configurable through fields in MSTPRI1, not the EDMA3CC QUEPRI register.
(3)
The priority for DSP MDMA and DSP CFG is controlled by fields in MSTPRI0 and not DSP.MDMAARBE.PRI
(DSP Bandwidth manager module).
(4)
The priority for DSP MDMA and DSP CFG is controlled by fields in MSTPRI0 and not DSP.MDMAARBE.PRI
(DSP Bandwidth manager module).
(5)
This peripheral is not supported on the C6745 DSP.
(6)
LCDC traffic is typically real-time sensitive, therefore, the default priority of 5, which is lower as compared to the default priority of
several masters, is not recommended. You should reconfigure LCDC priority to the highest or equal to other high-priority masters
in an application to ensure that throughput/latency requirements for LCDC are met.
Table 10-3. Default Master Priority
Master Default Priority
(1)
Master Priority Register
PRU0 0 MSTPRI1
PRU1 0 MSTPRI1
EDMA3TC0
(2)
0 MSTPRI1
EDMA3TC1 0 MSTPRI1
DSP MDMA
(3)
2 MSTPRI0
DSP CFG
(4)
2 MSTPRI0
EMAC 4 MSTPRI2
USB2.0 CFG 4 MSTPRI2
USB2.0 DMA 4 MSTPRI2
USB1.1
(5)
4 MSTPRI2
LCDC
(5) (6)
5 MSTPRI2
HPI
(5)
6 MSTPRI2
10.4 Interrupt Support
10.4.1 Interrupt Events and Requests
The SYSCFG module generates two interrupts: an address error interrupt (BOOTCFG_ADDR_ERR) and
a protection interrupt (BOOTCFG_PROT_ERR). The BOOTCFG_ADDR_ERR is generated when there is
an addressing violation due to an access to a non-existent location in the SYSCFG register space. The
BOOTCFG_PROT_ERR interrupt is generated when there is a protection violation of either in the defined
ranges or to the SYSCFG registers. It is required to write a value of 0 to the end of interrupt register (EOI)
after the software has processed the SYSCFG interrupt, this acts as an acknowledgement of completion
of the SYSCFG interrupt so that the module can reliably generate subsequent interrupts.
The transfer parameters that caused the violation are saved in the fault address register (FLTADDRR) and
the fault status register (FLTSTAT).
10.4.2 Interrupt Multiplexing
The interrupts from the SYSCFG module are combined with the interrupts from the MPU module into a
single interrupt called MPU_BOOTCFG_ERR. The combined interrupt is routed to the DSP interrupt
controller.
10.4.3 Host-DSP Communication Interrupts
The SYSCFG module also has a set of registers, the chip signal register (CHIPSIG) and the chip signal
clear register (CHIPSIG_CLR), to facilitate host-to-processor communication. This is generally used to
allow an external host and the DSP to coordinate.
Either of the processors can set specific bits in this SYSCFG register, which in turn can interrupt the other
processor, if the interrupts have been appropriately enabled in the processor’s interrupt controller.