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SPRUH91D–March 2013–Revised September 2016
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EMAC/MDIO Module
17.2.14 Reset Considerations
17.2.14.1 Software Reset Considerations
Peripheral clock and reset control is done through the Power and Sleep Controller (PSC) module included
with the device. For more on how the EMAC, MDIO, and EMAC control module are disabled or placed in
reset at runtime from the registers located in the PSC module, see Section 27.2.16.
With the EMAC still in reset (PSC in the default state):
1. Program the PINMUX register(s) as required for the desired interface (MII or RMII), see the Pin
Multiplexing Control Registers (PINMUX0-PINMUX19) in the System Configuration (SYSCFG) Module
chapter and your device-specific data manual for details.
2. Program the PSC to enable the EMAC. For information on how to enable the EMAC peripheral from
the PSC, see the Power and Sleep Controller (PSC) chapter.
Within the peripheral itself, the EMAC component of the Ethernet MAC peripheral can be placed in a reset
state by writing to the soft reset register (SOFTRESET). Writing a 1 to the SOFTRESET bit, causes the
EMAC logic to be reset and the register values to be set to their default values. Software reset occurs
when the receive and transmit DMA controllers are in an idle state to avoid locking up the configuration
bus; it is the responsibility of the software to verify that there are no pending frames to be transferred.
After writing a 1 to the SOFTRESET bit, it may be polled to determine if the reset has occurred. If a 1 is
read, the reset has not yet occurred; if a 0 is read, then a reset has occurred.
After a software reset operation, all the EMAC registers need to be reinitialized for proper data
transmission, including the FULLDUPLEX bit setting in the MAC control register (MACCONTROL).
Unlike the EMAC module, the MDIO and EMAC control modules cannot be placed in reset from a register
inside their memory map.
17.2.14.2 Hardware Reset Considerations
When a hardware reset occurs, the EMAC peripheral has its register values reset and all the components
return to their default state. After the hardware reset, the EMAC needs to be initialized before being able
to resume its data transmission, as described in Section 27.2.19.
A hardware reset is the only means of recovering from the error interrupts (HOSTPEND), which are
triggered by errors in packet buffer descriptors. Before doing a hardware reset, you should inspect the
error codes in the MAC status register (MACSTATUS) that gives information about the type of software
error that needs to be corrected. For detailed information on error interrupts, see Section 17.2.16.1.4.
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