Registers
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SPRUH91D–March 2013–Revised September 2016
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EMAC/MDIO Module
17.3.3.48 Transmit Channel Completion Pointer Registers (TX0CP-TX7CP)
The transmit channel 0-7 completion pointer register (TXnCP) is shown in Figure 17-86 and described in
Table 17-85.
Figure 17-86. Transmit Channel n Completion Pointer Register (TXnCP)
31 0
TXnCP
R/W-x
LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset
Table 17-85. Transmit Channel n Completion Pointer Register (TXnCP) Field Descriptions
Bit Field Value Description
31-0 TXnCP 0-FFFF FFFFh Transmit channel n completion pointer register is written by the host with the buffer descriptor
address for the last buffer processed by the host during interrupt processing. The EMAC uses the
value written to determine if the interrupt should be deasserted.
17.3.3.49 Receive Channel Completion Pointer Registers (RX0CP-RX7CP)
The receive channel 0-7 completion pointer register (RXnCP) is shown in Figure 17-87 and described in
Table 17-86.
Figure 17-87. Receive Channel n Completion Pointer Register (RXnCP)
31 0
RXnCP
R/W-x
LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset
Table 17-86. Receive Channel n Completion Pointer Register (RXnCP) Field Descriptions
Bit Field Value Description
31-0 RXnCP 0-FFFF FFFFh Receive channel n completion pointer register is written by the host with the buffer descriptor
address for the last buffer processed by the host during interrupt processing. The EMAC uses the
value written to determine if the interrupt should be deasserted.
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