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SPRUH91D–March 2013–Revised September 2016
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External Memory Interface B (EMIFB)
Table 19-10. Description of the SDRAM Configuration 2 Register (SDCFG2)
Parameter Description
PASR Partial Array Self Refresh. These bits get loaded into the Extended Mode Register of a mobile SDRAM
during initialization. A write to this field will cause the EMIFB to start the SDRAM initialization sequence.
ROWSIZE Row Size. Defines the number of row address bits of connected SDRAM devices. This bit is used only in
case of mobile SDRAM. A write to this field will cause the EMIFB to start the SDRAM initialization sequence.
19.2.6.4 SDRAM/mobile SDRAM Auto-Initialization Sequence
The EMIFB automatically performs an SDRAM initialization sequence, regardless of whether it is
interfaced to an SDRAM device, when the following event occurs:
• A write is performed to any of the two least significant bytes of the SDRAM configuration register
(SDCFG)
• In case of mobile SDR, initialization sequence also starts when a write is performed to SDRAM
configuration 2 register (SDCFG2)
An SDRAM/mobile SDR initialization sequence consists of the following steps:
1. First, software must set the SDREN bit (in case of mobile SDRAM, both SDREN and
MSDRAM_ENABLE should be set to 1) in the SDRAM configuration register (SDCFG) (assuming
clocking and pin multiplexing are already configured accordingly).
2. If the initialization sequence is activated by a write to SDCFG, and if any of the SDRAM banks are
open, the EMIFB issues a PRE command with EMB_A[10] held high to indicate all banks. This is done
so that the maximum ACTV to PRE timing for an SDRAM is not violated.
3. The EMIFB drives EMB_SDCKE high and begins continuously issuing NOP commands until eight
SDRAM refresh intervals have elapsed. An SDRAM refresh interval is equal to the value of the
REFRESH_RATE field of the SDRAM refresh control register (SDRFC), divided by the frequency of
EMB_CLK (REFRESH_RATE/f
CLK
). This step is used to avoid violating the Power-up constraint of most
SDRAM devices that requires 200 μs (sometimes 100 μs) between receiving stable Vdd and CLK and
the issuing of a PRE command. Depending on the frequency of EMB_CLK, this step may or may not
be sufficient to avoid violating the SDRAM constraint. See Section 19.2.6.5 for more information.
4. After the refresh intervals have elapsed, the EMIFB issues a PRE command with EMB_A[10] held high
to indicate all banks.
5. The EMIFB issues eight AUTO REFRESH commands.
6. If initialization sequence is of mobile SDRAM, EMIFB issues LMR command with EMB_A[6:0] pins set
as described in Table 19-11.
7. Then, EMIFB issues the LMR command with the EMB_A[9:0] pins set as described in Table 19-12.
This step is executed for both SDRAM/mobile SDRAM.
8. Finally, the EMIFB performs an auto refresh cycle, which consists of the following steps:
(a) Issuing a PRE command with EMB_A[10] held high if any banks are open
(b) Issuing a REF command
(c) Interface is idle (awaiting access)
Table 19-11. mobile SDRAM LOAD MODE REGISTER Command
A[6:5] A[4:3] A[2:0]
0 (SDRAM drive strength; 0= full
drive strength)
0 (Internal Temperature
Compensated Self Refresh)
These bits are set according to the PASR field in the
SDRAM configuration 2 register (SDCFG2).
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