Introduction
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SPRUH91D–March 2013–Revised September 2016
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Phase-Locked Loop Controller (PLLC)
7.1 Introduction
This device has one phase-locked loop (PLL) controller, PLL0, that provides a clock to different parts of
the system. PLL0 provides clocks (through various dividers) to most of the components of the device.
The PLL0 provides the following:
• Glitch-Free Transitions (on changing clock settings)
• Domain Clocks Alignment
• Clock Gating
• PLL power-down
The various clock outputs given by the controller are as follows:
• Domain Clocks: SYSCLK [1:n]
• Auxiliary Clock from reference clock source: AUXCLK
Various dividers that can be used are as follows:
• Pre-PLL Divider: PREDIV
• Post-PLL Divider: POSTDIV
• SYSCLK Divider: D1, …, Dn
Various other controls supported are as follows:
• PLL Multiplier Control: PLLM
• Software programmable PLL Bypass: PLLEN
7.2 PLL0 Control
PLL0 supplies the primary system clock. Software controls the PLL0 operation through the system PLL
controller 0 (PLLC0) registers. Figure 7-1 shows the PLL0 in the device.
AUXCLK is the clock provided to the fixed clock domain.
The PLL0 multiplier is controlled by the PLLM bits in the PLL multiplier control register (PLLM) and is set
to a default value of 0000 0013h at power-up, resulting in a PLL multiplier of 20×. The PLL0 output clock
may be divided-down for slower device operation using the PLLC0 post-divider. This divider defaults to a
/2 value, but may be modified by software (RATIO bit in POSTDIV) to achieve lower power device
operation. These default settings yield a 300-MHz PLL output clock when using a 30-MHz clock source.
The PLL0 multiplier may be modified by software.
At power-up, PLL0 is powered-down/disabled and must be powered-up by software through the
PLLPWRDN bit in the PLL control register (PLLCTL). The system operates in bypass mode by default and
the system clock (OSCIN) is provided directly from an input reference clock (square wave or internal
oscillator) selected by the CLKMODE bit in PLLCTL. Once the PLL is powered-up and locked, software
can switch the device to PLL mode operation (set the PLLEN bit in PLLCTL to 1).
Registers used in PLLC0 are listed in Section 7.4.
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