Introduction
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SPRUH91D–March 2013–Revised September 2016
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Power and Sleep Controller (PSC)
8.1 Introduction
The Power and Sleep Controllers (PSC) are responsible for managing transitions of system power on/off,
clock on/off, resets (device level and module level). It is used primarily to provide granular power control
for on chip modules (peripherals and CPU). A PSC module consists of a Global PSC (GPSC) and a set of
Local PSCs (LPSCs). The GPSC contains memory mapped registers, PSC interrupts, a state machine for
each peripheral/module it controls. An LPSC is associated with every module that is controlled by the PSC
and provides clock and reset control. Many of the operations of the PSC are transparent to user
(software), such as power on and reset control. However, the PSC module(s) also provide you with
interface to control several important power, clock and reset operations. The module level power, clock
and reset operations managed and controlled by the PSC are the focus of this chapter.
The PSC includes the following features:
• Manages chip power-on/off
• Provides a software interface to:
– Control module clock enable/disable
– Control module reset
– Control CPU local reset
• Manages on-chip RAM sleep modes (for DSP memories and L3 RAM)
• Supports IcePick emulation features: power, clock and reset
8.2 Power Domain and Module Topology
This device includes two PSC modules. Each PSC module consists of an Always On power domain and
an additional pseudo/internal power domain that manages the sleep modes for the RAMs present in the
DSP subsystem and the L3 RAM , respectively.
Each PSC module controls clock states for several on the on chip modules, controllers and interconnect
components. Table 8-1 and Table 8-2 lists the set of peripherals/modules that are controlled by the PSC,
the power domain they are associated with, the LPSC assignment and the default (power-on reset)
module states. See the device-specific data manual for the peripherals available on a given device. The
module states and terminology are defined in Section 8.2.2.
Even though there are 2 PSC modules with 2 power domains each on the device, both PSC modules and
all the power domains are powered by the CVDD pins of the device. All power domains are on when the
chip is powered on. There is no provision to remove power externally for the non Always On domains, that
is, the pseudo/internal power domains.
There are a few modules/peripherals on the device that do not have a LPSC assigned to them. These
modules do not have their module reset/clocks controlled by the PSC module. The decision to assign an
LPSC to a module on a device is primarily based on whether or not disabling the clocks to a module will
result in significant power savings. This typically depends on the size and the frequency of operation of the
module.
Table 8-1. PSC0 Default Module Configuration
LPSC Number Module Name Power Domain Default Module State Auto Sleep/Wake Only
0 EDMA3 Channel Controller AlwaysON (PD0) SwRstDisable —
1 EDMA3 Transfer Controller 0 AlwaysON (PD0) SwRstDisable —
2 EDMA3 Transfer Controller 1 AlwaysON (PD0) SwRstDisable —
3 EMIFA (BR7) AlwaysON (PD0) SwRstDisable —
4 SPI0 AlwaysON (PD0) SwRstDisable —
5 MMC/SD0 AlwaysON (PD0) SwRstDisable —
6-8 Not Used — — —
9 UART0 AlwaysON (PD0) SwRstDisable —
10 Not Used — — —
11 SCR1 (BR4) AlwaysON (PD0) Enable Yes
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