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SPRUH91D–March 2013–Revised September 2016
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External Memory Interface A (EMIFA)
(1)
The EMA_WAIT pin is not available on all devices; therefore, this field is reserved on those devices.
Table 18-17. Description of the EMIFA Interrupt Mask Set Register (INTMSKSET)
Parameter Description
WR_MASK_SET Wait Rise Mask Set.
Writing a 1 enables an interrupt to be generated when a rising edge on EMA_WAIT
(1)
occurs while in
NAND Flash Mode
AT_MASK_SET Asynchronous Timeout Mask Set.
Writing a 1 to this bit enables an interrupt to be generated when an Asynchronous Timeout occurs.
Table 18-18. Description of the EMIFA Interrupt Mast Clear Register (INTMSKCLR)
Parameter Description
WR_MASK_CLR Wait Rise Mask Clear.
Writing a 1 to this bit disables the interrupt, clearing the WR_MASK_SET bit in the EMIFA
interrupt mask set register (INTMSKSET).
AT_MASK_CLR Asynchronous Timeout Mask Clear.
Writing a 1 to this bit prevents an interrupt from being generated when an Asynchronous Timeout
occurs.
18.2.5.4 Read and Write Operations in Normal Mode
Normal Mode is the asynchronous interface's default mode of operation. It is selected when the SS bit in
the asynchronous n configuration register (CEnCFG) is cleared to 0. In this mode, the EMA_WE_DQM
pins operate as byte enables. Section 18.2.5.4.1 and Section 18.2.5.4.2 explain the details of read and
write operations while in Normal Mode.
18.2.5.4.1 Asynchronous Read Operations (Normal Mode)
NOTE: During the entirety of an asynchronous read operation, the EMA_WE pin is driven high.
An asynchronous read is performed when any of the requesters mentioned in Section 18.2.2 request a
read from the attached asynchronous memory. After the request is received, a read operation is initiated
once it becomes the EMIFA's highest priority task, according to the priority scheme detailed in
Section 18.2.12. In the event that the read request cannot be serviced by a single access cycle to the
external device, multiple access cycles will be performed by the EMIFA until the entire request is fulfilled.
The details of an asynchronous read operation in Normal Mode are described in Table 18-19. Also,
Figure 18-10 shows an example timing diagram of a basic read operation.
Table 18-19. Asynchronous Read Operation in Normal Mode
Time Interval Pin Activity in Normal Mode
Turnaround
period
Once the read operation becomes the highest priority task for the EMIFA, the EMIFA waits for the programmed
number of turn-around cycles before proceeding to the setup period of the operation. The number of wait cycles is
taken directly from the TA field of the asynchronous n configuration register (CEnCFG). There are two exceptions
to this rule:
• If the current read operation was directly proceeded by another read operation to the same chip select, no
turnaround cycles are inserted.
After the EMIFA has waited for the turnaround cycles to complete, it again checks to make sure that the read
operation is still its highest priority task. If so, the EMIFA proceeds to the setup period of the operation. If it is no
longer the highest priority task, the EMIFA terminates the operation.
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