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SPRUH91D–March 2013–Revised September 2016
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External Memory Interface A (EMIFA)
Table 18-16. Description of the Asynchronous Wait Cycle Configuration Register (AWCC)
(1)
(continued)
Parameter Description
MAX_EXT_WAIT Maximum Extended Wait Cycles.
This field configures the number of EMIFA clock cycles the EMIFA will wait for the EMA_WAIT pin
to be deactivated during the strobe period of an access cycle. The maximum number of EMIFA
clock cycles it will wait is determined by the following formula:
Maximum Extended Wait Cycles = (MAX_EXT_WAIT + 1) × 16
If the EMA_WAIT pin is not deactivated within the time specified by this field, the EMIFA resumes
the access cycle, registering whatever data is on the bus and proceeding to the hold period of the
access cycle. This situation is referred to as an Asynchronous Timeout. An Asynchronous
Timeout generates an interrupt, if it has been enabled in the EMIFA interrupt mask set register
(INTMSKSET). Refer to Section 18.2.8.1 for more information about the EMIFA interrupts.
Extended Wait Mode should not be used while in NAND Flash Mode.
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