www.ti.com
Registers
391
SPRUH91D–March 2013–Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
14.4.7.2 Event-Trigger Prescale Register (ETPS)
The event-trigger prescale register (ETPS) is shown in Figure 14-88 and described in Table 14-80.
Figure 14-88. Event-Trigger Prescale Register (ETPS)
15 4 3 2 1 0
Reserved INTCNT INTPRD
R-0 R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-80. Event-Trigger Prescale Register (ETPS) Field Descriptions
Bits Name Value Description
15-4 Reserved 0 Reserved
3-2 INTCNT 0-3h ePWM Interrupt Event (EPWMx_INT) Counter Register. These bits indicate how many selected
ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is
generated. If interrupts are disabled, ETSEL[INT] = 0 or the interrupt flag is set, ETFLG[INT] = 1, the
counter will stop counting events when it reaches the period value ETPS[INTCNT] = ETPS[INTPRD].
0 No events have occurred.
1h 1 event has occurred.
2h 2 events have occurred.
3h 3 events have occurred.
1-0 INTPRD 0-3h ePWM Interrupt (EPWMx_INT) Period Select. These bits determine how many selected
ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated, the interrupt
must be enabled (ETSEL[INT] = 1). If the interrupt status flag is set from a previous interrupt
(ETFLG[INT] = 1) then no interrupt will be generated until the flag is cleared via the ETCLR[INT] bit.
This allows for one interrupt to be pending while another is still being serviced. Once the interrupt is
generated, the ETPS[INTCNT] bits will automatically be cleared.
Writing a INTPRD value that is the same as the current counter value will trigger an interrupt if it is
enabled and the status flag is clear.
Writing a INTPRD value that is less than the current counter value will result in an undefined state.
If a counter event occurs at the same instant as a new zero or non-zero INTPRD value is written, the
counter is incremented.
0 Disable the interrupt event counter. No interrupt will be generated and ETFRC[INT] is ignored.
1h Generate an interrupt on the first event INTCNT = 01 (first event)
2h Generate interrupt on ETPS[INTCNT] = 1,0 (second event)
3h Generate interrupt on ETPS[INTCNT] = 1,1 (third event)
To Next Page
Loading...
