Texas Instruments TMS320C6745 DSP - PLL Controller Divider 7 Register (PLLDIV7); PLL Controller Divider 7 Register (PLLDIV7) Field Descriptions

www.ti.com PLLC Registers
129
SPRUH91D–March 2013–Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Phase-Locked Loop Controller (PLLC)
7.4.13 PLL Controller Divider 7 Register (PLLDIV7)
The PLL controller divider 7 register (PLLDIV7) is shown in Figure 7-14 and described in Table 7-15.
Divider 7 controls the divider for SYSCLK7.
Figure 7-14. PLL Controller Divider 7 Register (PLLDIV7)
31 16
Reserved
R-0
15 14 5 4 0
D7EN Reserved RATIO
R/W-1 R-0 R/W-5h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-15. PLL Controller Divider 7 Register (PLLDIV7) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Reserved
15 D7EN Divider Enable.
0 Disable
1 Enable
14-5 Reserved 0 Reserved
4-0 RATIO 0-1Fh Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 5 (PLL divide by 6).