Texas Instruments TMS320C6745 DSP - GPIO Bank 8 Clear Rise Trigger Register (CLR_FAL_TRIG8); GPIO Clear Falling Edge Interrupt Register (Clr_Fal_Trign) Field Descriptions

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SPRUH91D–March 2013–Revised September 2016
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General-Purpose Input/Output (GPIO)
Figure 20-48. GPIO Bank 8 Clear Rise Trigger Register (CLR_FAL_TRIG8)
31 16
Reserved
R/W-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GP8P15 GP8P14 GP8P13 GP8P12 GP8P11 GP8P10 GP8P9 GP8P8 GP8P7 GP8P6 GP8P5 GP8P4 GP8P3 GP8P2 GP8P1 GP8P0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 20-13. GPIO Clear Falling Edge Interrupt Register (CLR_FAL_TRIGn) Field Descriptions
Bit Field Value Description
31-0 GPkPj Disable falling edge interrupt detection on GPk[j]. Reading the GPkPj bit in either SET_FAL_TRIGn or
CLR_FAL_TRIGn always returns an indication of whether the falling edge interrupt generation function
is enabled for GPk[j]. Therefore, this bit will be one in both registers if the function is enabled, and zero
in both registers if the function is disabled.
0 No effect.
1 No interrupt is caused by a high-to-low transition on GPk[j].