Texas Instruments TMS320C6745 DSP - Access Types Selectable with the UHPI_HCNTL Signals; Cycle Types Selectable with the UHPI_HCNTL and UHPI_HR;W Signals

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SPRUH91D–March 2013–Revised September 2016
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Host Port Interface (HPI)
21.2.6.5 UHPI_HCNTL[1:0] and UHPI_HR/W: Indicating the Cycle Type
The cycle type consists of:
• The access type that the host selects by driving the appropriate levels on the UHPI_HCNTL[1:0] pins
of the HPI. Table 21-4 describes the four available access types.
• The transfer direction that the host selects with the UHPI_HR/W pin. The host must drive the
UHPI_HR/W signal high (read) or low (write).
A summary of cycle types is in Table 21-5. The HPI samples the UHPI_HCNTL levels at the falling edge
of the internal strobe signal HSTRB.
Table 21-4. Access Types Selectable With the UHPI_HCNTL Signals
UHPI_HCNTL1 UHPI_HCNTL0 Access Type
0 0 HPIC access. The host requests to access the HPI control register
(HPIC).
0 1 HPID access with autoincrementing. The host requests to access the
HPI data register (HPID) and to have the appropriate HPI address register
(HPIAR and/or HPIAW) automatically incremented by 1 after the access.
1 0 HPIA access. The host requests to access the appropriate HPI address
register (HPIAR and/or HPIAW).
1 1 HPID access without autoincrementing. The host requests to access
the HPI data register (HPID) but requests no automatic post-increment of
the HPI address register.
Table 21-5. Cycle Types Selectable With the UHPI_HCNTL and UHPI_HR/W Signals
UHPI_HCNTL1 UHPI_HCNTL0 UHPI_HR/W Cycle Type
0 0 0 HPIC write cycle
0 0 1 HPIC read cycle
0 1 0 HPID write cycle with autoincrementing
0 1 1 HPID read cycle with autoincrementing
1 0 0 HPIA write cycle
1 0 1 HPIA read cycle
1 1 0 HPID write cycle without autoincrementing
1 1 1 HPID read cycle without autoincrementing
21.2.6.6 UHPI_HHWIL: Identifying the First and Second Halfwords in Multiplexed Mode Transfers
Each host cycle consists of two consecutive halfword transfers. For each transfer, the host must specify
the cycle type with UHPI_HCNTL[1:0] and UHPI_HR/W, and the host must use UHPI_HHWIL to indicate
whether the first or second halfword is being transferred. For HPID and HPIA accesses, UHPI_HHWIL
must always be driven low for the first halfword transfer and high for the second halfword transfer. Results
are undefined if the sequence is broken. For examples of using UHPI_HHWIL, see Section 21.2.6.7.
When the host sends the two halfwords of a 32-bit word in this manner, the host can send the most-
significant and the least-significant halfwords of the word in either order (most-significant halfword first or
most-significant halfword second). However, the host must inform the HPI of the selected order before
beginning the host cycle. This is done by programming the halfword order (HWOB) bit in HPIC. Although
HWOB is written at bit 0 in HPIC, its current value is readable at both bit 0 and bit 8 (HWOBSTAT). Thus,
the host can determine the current halfword order configuration by checking the least-significant bit of
either half of HPIC.