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Registers
393
SPRUH91D–March 2013–Revised September 2016
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Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
14.4.7.5 Event-Trigger Force Register (ETFRC)
The event-trigger force register (ETFRC) is shown in Figure 14-91 and described in Table 14-83.
Figure 14-91. Event-Trigger Force Register (ETFRC)
15 1 0
Reserved INT
R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 14-83. Event-Trigger Force Register (ETFRC) Field Descriptions
Bits Name Value Description
15-1 Reserved 0 Reserved
0 INT INT Force Bit. The interrupt will only be generated if the event is enabled in the ETSEL register. The
INT flag bit will be set regardless.
0 Writing 0 to this bit will be ignored. Always reads back a 0.
1 Generates an interrupt on EPWMxINT and set the INT flag bit. This bit is used for test purposes.
14.4.8 High-Resolution PWM Submodule Registers
Table 14-84 lists the memory-mapped registers for the high-resolution PWM submodule. See your device-
specific data manual for the memory address of these registers. All other register offset addresses not
listed in Table 14-84 should be considered as reserved locations and the register contents should not be
modified.
Table 14-84. High-Resolution PWM Submodule Registers
Offset Acronym Register Description Section
4h TBPHSHR Time-Base Phase High-Resolution Register Section 14.4.8.1
10h CMPAHR Counter-Compare A High-Resolution Register Section 14.4.8.2
1040h HRCNFG HRPWM Configuration Register Section 14.4.8.3
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