Texas Instruments TMS320C6745 DSP - Clock Status Register (CKSTAT); Clock Status Register (CKSTAT) Field Descriptions

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SPRUH91D–March 2013–Revised September 2016
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Phase-Locked Loop Controller (PLLC)
7.4.21 Clock Status Register (CKSTAT)
The clock status register (CKSTAT) is shown in Figure 7-22 and described in Table 7-23. Clock status for
all clocks, except SYSCLKn.
(1)
This bit is not supported and is Reserved on the C6745 DSP.
Figure 7-22. Clock Status Register (CKSTAT)
31 16
Reserved
R-0
15 1 0
Reserved OBSON
(1)
AUXEN
R-0 R-1 R-1
LEGEND: R = Read only; -n = value after reset
Table 7-23. Clock Status Register (CKSTAT) Field Descriptions
Bit Field Value Description
31-2 Reserved 0 Reserved
1 OBSON OBSCLK on status. OBSCLK is controlled in the oscillator divider 1 register (OSCDIV) and by the
OBSEN bit in the clock enable control register (CKEN). This bit is not supported and is Reserved on the
C6745 DSP.
0 OBSCLK is off.
1 OBSCLK is on.
0 AUXEN AUXCLK on status. AUXCLK is controlled by the AUXEN bit in the clock enable control register
(CKEN).
0 AUXCLK is off.
1 AUXCLK is on.