Texas Instruments TMS320C6745 DSP - Performance Counter Master Region Select Register (PCMRS); Performance Counter Master Region Select Register (PCMRS) Field Descriptions

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SPRUH91D–March 2013–Revised September 2016
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External Memory Interface B (EMIFB)
19.4.9 Performance Counter Master Region Select Register (PCMRS)
The performance counter master region select register (PCMRS) is shown in Figure 19-23 and described
in Table 19-35.
Figure 19-23. Performance Counter Master Region Select Register (PCMRS)
31 24 23 20 19 16
MST_ID2 Reserved REGION_SEL2
R/W-0 R-0 R/W-0
15 8 7 4 3 0
MST_ID1 Reserved REGION_SEL1
R/W-0 R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-35. Performance Counter Master Region Select Register (PCMRS) Field Descriptions
Bit Field Value Description
31-24 MST_ID2 0-FFh Master ID for performance counter 2 register (PC2). For the Master ID value for master peripherals
in the device, see the System Configuration (SYSCFG) Module chapter.
23-20 Reserved 0 Any writes to these bit(s) must always have a value of 0.
19-16 REGION_SEL2 0-Fh Region select for performance counter 2 register (PC2).
0 PC2 counts total SDRAM accesses.
1h-6h Reserved
7h PC2 counts total EMIFB memory-mapped register accesses.
8h-Fh Reserved
15-8 MST_ID1 0-FFh Master ID for performance counter 1 register (PC1). For the Master ID value for master peripherals
in the device, see the System Configuration (SYSCFG) Module chapter.
7-4 Reserved 0 Any writes to these bit(s) must always have a value of 0.
3-0 REGION_SEL1 0-Fh Region select for performance counter 1 register (PC1).
0 PC1 counts total SDRAM accesses.
1h-6h Reserved
7h PC1 counts total EMIFB memory-mapped register accesses.
8h-Fh Reserved