Registers
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SPRUH91D–March 2013–Revised September 2016
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EMAC/MDIO Module
17.3.3 EMAC Module Registers
Table 17-37 lists the memory-mapped registers for the EMAC. See your device-specific data manual for
the memory address of these registers.
Table 17-37. Ethernet Media Access Controller (EMAC) Registers
Offset Acronym Register Description Section
0h TXREVID Transmit Revision ID Register Section 17.3.3.1
4h TXCONTROL Transmit Control Register Section 17.3.3.2
8h TXTEARDOWN Transmit Teardown Register Section 17.3.3.3
10h RXREVID Receive Revision ID Register Section 17.3.3.4
14h RXCONTROL Receive Control Register Section 17.3.3.5
18h RXTEARDOWN Receive Teardown Register Section 17.3.3.6
80h TXINTSTATRAW Transmit Interrupt Status (Unmasked) Register Section 17.3.3.7
84h TXINTSTATMASKED Transmit Interrupt Status (Masked) Register Section 17.3.3.8
88h TXINTMASKSET Transmit Interrupt Mask Set Register Section 17.3.3.9
8Ch TXINTMASKCLEAR Transmit Interrupt Clear Register Section 17.3.3.10
90h MACINVECTOR MAC Input Vector Register Section 17.3.3.11
94h MACEOIVECTOR MAC End Of Interrupt Vector Register Section 17.3.3.12
A0h RXINTSTATRAW Receive Interrupt Status (Unmasked) Register Section 17.3.3.13
A4h RXINTSTATMASKED Receive Interrupt Status (Masked) Register Section 17.3.3.14
A8h RXINTMASKSET Receive Interrupt Mask Set Register Section 17.3.3.15
ACh RXINTMASKCLEAR Receive Interrupt Mask Clear Register Section 17.3.3.16
B0h MACINTSTATRAW MAC Interrupt Status (Unmasked) Register Section 17.3.3.17
B4h MACINTSTATMASKED MAC Interrupt Status (Masked) Register Section 17.3.3.18
B8h MACINTMASKSET MAC Interrupt Mask Set Register Section 17.3.3.19
BCh MACINTMASKCLEAR MAC Interrupt Mask Clear Register Section 17.3.3.20
100h RXMBPENABLE Receive Multicast/Broadcast/Promiscuous Channel Enable
Register
Section 17.3.3.21
104h RXUNICASTSET Receive Unicast Enable Set Register Section 17.3.3.22
108h RXUNICASTCLEAR Receive Unicast Clear Register Section 17.3.3.23
10Ch RXMAXLEN Receive Maximum Length Register Section 17.3.3.24
110h RXBUFFEROFFSET Receive Buffer Offset Register Section 17.3.3.25
114h RXFILTERLOWTHRESH Receive Filter Low Priority Frame Threshold Register Section 17.3.3.26
120h RX0FLOWTHRESH Receive Channel 0 Flow Control Threshold Register Section 17.3.3.27
124h RX1FLOWTHRESH Receive Channel 1 Flow Control Threshold Register Section 17.3.3.27
128h RX2FLOWTHRESH Receive Channel 2 Flow Control Threshold Register Section 17.3.3.27
12Ch RX3FLOWTHRESH Receive Channel 3 Flow Control Threshold Register Section 17.3.3.27
130h RX4FLOWTHRESH Receive Channel 4 Flow Control Threshold Register Section 17.3.3.27
134h RX5FLOWTHRESH Receive Channel 5 Flow Control Threshold Register Section 17.3.3.27
138h RX6FLOWTHRESH Receive Channel 6 Flow Control Threshold Register Section 17.3.3.27
13Ch RX7FLOWTHRESH Receive Channel 7 Flow Control Threshold Register Section 17.3.3.27
140h RX0FREEBUFFER Receive Channel 0 Free Buffer Count Register Section 17.3.3.28
144h RX1FREEBUFFER Receive Channel 1 Free Buffer Count Register Section 17.3.3.28
148h RX2FREEBUFFER Receive Channel 2 Free Buffer Count Register Section 17.3.3.28
14Ch RX3FREEBUFFER Receive Channel 3 Free Buffer Count Register Section 17.3.3.28
150h RX4FREEBUFFER Receive Channel 4 Free Buffer Count Register Section 17.3.3.28
154h RX5FREEBUFFER Receive Channel 5 Free Buffer Count Register Section 17.3.3.28
158h RX6FREEBUFFER Receive Channel 6 Free Buffer Count Register Section 17.3.3.28
15Ch RX7FREEBUFFER Receive Channel 7 Free Buffer Count Register Section 17.3.3.28
160h MACCONTROL MAC Control Register Section 17.3.3.29
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