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PLL0 Control
119
SPRUH91D–March 2013–Revised September 2016
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Phase-Locked Loop Controller (PLLC)
7.2.2 Steps for Changing PLL0 Domain Frequency
Refer to the appropriate subsection on how to program the PLL0/Core Domain clocks:
• If the PLL is powered down (PLLPWRDN bit in PLLCTL is set to 1), follow the full PLL initialization
procedure in Section 7.2.2.1 to initialize the PLL.
• If the PLL is not powered down (PLLPWRDN bit in PLLCTL is cleared to 0), follow the sequence in
Section 7.2.2.2 to change the PLL multiplier.
• If the PLL is already running at a desired multiplier and you only want to change the SYSCLK dividers,
follow the sequence in Section 7.2.2.3.
Note that the PLL is powered down after a Power-on Reset (POR). The PLL is not powered down after a
Warm Reset (RESET), but the PLLEN bit in PLLCTL is cleared to 0 (bypass mode) and the PLLDIVx
registers are reset to default values.
7.2.2.1 Initializing PLL Mode from PLL Power Down
If the PLL is powered down (PLLPWRDN bit in PLLCTL is set to 1), perform the following procedure to
initialize the PLL:
1. Clear the PLLEN bit in PLLCTL to 0 (select PLL Bypass mode) and reset the PLL by clearing PLLRST
bit in PLLCTL. Wait for 4 OSCIN cycles to ensure PLLC switches to bypass mode properly.
2. Select the clock mode by programming the CLKMODE bit in PLLCTL.
(a) Clear the PLLENSRC bit in PLLCTL to 0 to allow PLLCTL.PLLEN to take effect.
(b) PLLCTL.EXTCLKSRC should be left to 0.
3. Clear the PLLRST bit in PLLCTL to 0 (reset PLL).
4. Clear the PLLPWRDN bit in PLLCTL to 0 to bring the PLL out of power-down mode.
5. Program the required multiplier value in PLLM. If desired to scale all the SYSCLK frequencies of a
given PLLC, program the POSTDIV ratio.
6. If necessary, program PLLDIVn registers to change the SYSCLK0 to SYSCLKn divide values:
(a) Check for GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in
progress.
(b) Program the RATIO field in PLLDIVx with the desired divide factors.
(c) Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition.
(d) Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of phase alignment).
7. Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset.
8. Wait for PLL to lock. See the device-specific data manual for PLL lock time.
9. Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode.
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