Texas Instruments TMS320C6745 DSP - Host Port Interface Write Address Register (HPIAW); Host Port Interface Read Address Register (HPIAR); Host Port Interface Write Address Register (HPIAW) Field Descriptions; Host Port Interface Read Address Register (HPIAR) Field Descriptions

www.ti.com Registers
889
SPRUH91D–March 2013–Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Host Port Interface (HPI)
21.3.9 Host Port Interface Write Address Register (HPIAW)
The HPI contains two 32-bit address registers: one for read operations (HPIAR) and one for write
operations (HPIAW). The host port interface write address register (HPIAW) is shown in Figure 21-26 and
described in Table 21-15. The HPI can be configured such that HPIAR and HPIAW act as a single 32-bit
HPIA (single-HPIA mode) or as two separate 32-bit HPIAs (dual-HPIA mode) from the perspective of the
host. For details about these HPIA modes, see Section 21.2.6.1.
Note that the addresses loaded into the HPI address registers can be configured by the HPIBYTEAD bit in
the chip configuration 1 register (CFGCHIP1) of the system configuration module. If byte address is
selected (HPIBYTEAD = 1), the address must be 32-bit word aligned (with the least-significant two bits
equal to zero).
Figure 21-26. Host Port Interface Write Address Register (HPIAW)
31 0
HPIAW
R-0000 8000h
LEGEND: R = Read only; -n = value after reset
Table 21-15. Host Port Interface Write Address Register (HPIAW) Field Descriptions
Bit Field Value Description
31-0 HPIAW 0-FFFF FFFFh Host port interface write address.
21.3.10 Host Port Interface Read Address Register (HPIAR)
The HPI contains two 32-bit address registers: one for read operations (HPIAR) and one for write
operations (HPIAW). The host port interface read address register (HPIAR) is shown in Figure 21-27 and
described in Table 21-16. The HPI can be configured such that HPIAR and HPIAW act as a single 32-bit
HPIA (single-HPIA mode) or as two separate 32-bit HPIAs (dual-HPIA mode) from the perspective of the
host. For details about these HPIA modes, see Section 21.2.6.1.
Note that the addresses loaded into the HPI address registers can be configured by the HPIBYTEAD bit in
the chip configuration 1 register (CFGCHIP1) of the system configuration module. If byte address is
selected (HPIBYTEAD = 1), the address must be 32-bit word aligned (with the least-significant two bits
equal to zero).
Figure 21-27. Host Port Interface Read Address Register (HPIAR)
31 0
HPIAR
R-0000 8000h
LEGEND: R = Read only; -n = value after reset
Table 21-16. Host Port Interface Read Address Register (HPIAR) Field Descriptions
Bit Field Value Description
31-0 HPIAR 0-FFFF FFFFh Host port interface read address.