Texas Instruments TMS320C6745 DSP - PLL Controller Divider 5 Register (PLLDIV5); PLL Controller Divider 6 Register (PLLDIV6); PLL Controller Divider 5 Register (PLLDIV5) Field Descriptions; PLL Controller Divider 6 Register (PLLDIV6) Field Descriptions

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SPRUH91D–March 2013–Revised September 2016
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Phase-Locked Loop Controller (PLLC)
7.4.11 PLL Controller Divider 5 Register (PLLDIV5)
The PLL controller divider 5 register (PLLDIV5) is shown in Figure 7-12 and described in Table 7-13.
Divider 5 controls the divider for SYSCLK5.
Figure 7-12. PLL Controller Divider 5 Register (PLLDIV5)
31 16
Reserved
R-0
15 14 5 4 0
D5EN Reserved RATIO
R/W-1 R-0 R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-13. PLL Controller Divider 5 Register (PLLDIV5) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Reserved
15 D5EN Divider Enable.
0 Disable
1 Enable
14-5 Reserved 0 Reserved
4-0 RATIO 0-1Fh Divider ratio. Divider Value = RATIO + 1. RATIO defaults 2 (PLL divide by 3).
7.4.12 PLL Controller Divider 6 Register (PLLDIV6)
The PLL controller divider 6 register (PLLDIV6) is shown in Figure 7-13 and described in Table 7-14.
Divider 6 controls the divider for SYSCLK6.
Figure 7-13. PLL Controller Divider 6 Register (PLLDIV6)
31 16
Reserved
R-0
15 14 5 4 0
D6EN Reserved RATIO
R/W-1 R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-14. PLL Controller Divider 6 Register (PLLDIV6) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Reserved
15 D6EN Divider Enable.
0 Disable
1 Enable
14-5 Reserved 0 Reserved
4-0 RATIO 0-1Fh Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 0 (PLL divide by 1).