Texas Instruments TMS320C6745 DSP - 16.1 Introduction; 16.1.1 Overview; 16.1.2 Features

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SPRUH91D–March 2013–Revised September 2016
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Enhanced Direct Memory Access (EDMA3) Controller
16.1 Introduction
16.1.1 Overview
The enhanced direct memory access (EDMA3) controller’s primary purpose is to service user-
programmed data transfers between two memory-mapped slave endpoints on the device. Typical usage
includes, but is not limited to:
• Servicing software driven paging transfers (for example, from external memory to internal device
memory
• Servicing event driven peripherals, such as a serial port
• Performing sorting or subframe extraction of various data structures
• Offloading data transfers from the main device CPU(s) or DSP(s) (See your device-specific data
manual for specific peripherals that are accessible via EDMA3. See the section on SCR connectivity in
your device-specific data manual for EDMA3 connectivity.)
The EDMA3 has a different architecture from the previous EDMA2 controller on the TMS320C621x/C671x
DSPs and TMS320C64x DSPs.
The EDMA3 controller consists of two principal blocks:
• EDMA3 channel controller: EDMA3CC
• EDMA3 transfer controller(s): EDMA3TCn
The EDMA3 channel controller serves as the user interface for the EDMA3 controller. The EDMA3CC
includes parameter RAM (PaRAM), channel control registers, and interrupt control registers. The
EDMA3CC serves to prioritize incoming software requests or events from peripherals, and submits
transfer requests (TR) to the EDMA3 transfer controller.
The EDMA3 transfer controllers are responsible for data movement. The transfer request packets (TRP)
submitted by the EDMA3CC contains the transfer context, based on which the transfer controller issues
read/write commands to the source and destination addresses programmed for a given transfer.
16.1.2 Features
The EDMA3 channel controller (EDMA3CC) has the following features:
• Fully orthogonal transfer description
– 3 transfer dimensions
– A-synchronized transfers: 1 dimension serviced per event
– AB-synchronized transfers: 2 dimensions serviced per event
– Independent indexes on source and destination
– Chaining feature allows 3-D transfer based on single event
• Flexible transfer definition
– Increment or constant addressing modes
– Linking mechanism allows automatic PaRAM set update. Useful for ping-pong type transfers, auto-
reload transfers.
– Chaining allows multiple transfers to execute with a single event
• Interrupt generation for:
– Transfer completion
– Error conditions (illegal addresses, illegal modes, exceeding queue threshold)
• Debug visibility
– Queue watermarking
– Error and status recording to facilitate debug
– Missed event detection
• 128 parameter RAM (PaRAM) entries
• 4 shadow regions