Texas Instruments TMS320C6745 DSP - EDMA3 CC Status Register (CCSTAT); EDMA3 CC Status Register (CCSTAT) Field Descriptions

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SPRUH91D–March 2013–Revised September 2016
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Enhanced Direct Memory Access (EDMA3) Controller
16.4.2.4.4 EDMA3CC Status Register (CCSTAT)
The EDMA3CC status register (CCSTAT) has a number of status bits that reflect which parts of the
EDMA3CC logic is active at any given instant of time. The CCSTAT is shown in Figure 16-60 and
described in Table 16-39.
Figure 16-60. EDMA3CC Status Register (CCSTAT)
31 24
Reserved
R-0
23 18 17 16
Reserved QUEACTV1 QUEACTV0
R-0 R-0 R-0
15 14 13 8
Reserved COMPACTV
R-0 R-0
7 5 4 3 2 1 0
Reserved ACTV WSTATACTV TRACTV QEVTACTV EVTACTV
R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 16-39. EDMA3CC Status Register (CCSTAT) Field Descriptions
Bit Field Value Description
31-18 Reserved 0 Reserved
17 QUEACTV1 Queue 1 active.
0 No events are queued in queue 1.
1 At least one TR is queued in queue 1.
16 QUEACTV0 Queue 0 active.
0 No events are queued in queue 0.
1 At least one TR is queued in queue 0.
15-14 Reserved 0 Reserved
13-8 COMPACTV 0-3Fh Completion request active. The COMPACTV field reflects the count for the number of completion
requests submitted to the transfer controllers. This count increments every time a TR is submitted
and is programmed to report completion (the TCINTEN or TCCCHEN bits in OPT in the parameter
entry associated with the TR are set to 1). The counter decrements for every valid TCC received
back from the transfer controllers. If at any time the count reaches a value of 63, the EDMA3CC will
not service any new TRs until the count is less then 63 (or return a transfer completion code from a
transfer controller, which would decrement the count).
0 No completion requests outstanding.
1h-3Fh Total of 1 completion request to 63 completion requests are outstanding.
7-5 Reserved 0 Reserved
4 ACTV Channel controller active. Channel controller active is a logical-OR of each of the *ACTV bits. The
ACTV bit remains high through the life of a TR.
0 Channel is idle.
1 Channel is busy.
3 WSTATACTV Write status interface active.
0 Write status req is idle and write status fifo is idle.
1 Either the write status request is active or additional write status responses are pending in the write
status fifo.
2 TRACTV Transfer request active.
0 Transfer request processing/submission logic is inactive.
1 Transfer request processing/submission logic is active.