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Peripheral Clocking
109
SPRUH91D–March 2013–Revised September 2016
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Device Clocking
6.3.2 EMIFB Clocking
The EMIFB requires two input clocks to source VCLK and MCLK (see Figure 6-3):
• VCLK is sourced from SYSCLK2 that clocks the peripheral bus interface of EMIFB
• MCLK, which sets the clock rate for the I/O clock (EMB_CLK), is sourced from either SYSCLK5 or
DIV4P5. The EMB_CLKSRC bit in the chip configuration 3 register (CFGCHIP3) of the System
Configuration Module controls whether SYSCLK5 or DIV4P5 is selected as the clock source for MCLK.
Selecting the appropriate clock source for MCLK is determined by the desired clock rate of the memory
clock, EMB_CLK. Table 6-5 shows example PLL register settings and the resulting DIV4P5 and SYSCLK5
frequencies based on the OSCIN reference clock frequency of 25 MHz. From these example
configurations, the following observations can be made:
• To achieve the maximum frequency (133 MHz) supported by EMIFB and the typical CPU frequency of
300 MHz, the output of the PLL multiplier should be set to be 600 MHz and the EMB_CLK source
should be set to DIV4P5.
• The frequency of the DIV4P5 clock is fixed at the output frequency of the PLL multiplier block divided
by 4.5.
• The PLLDIV5 block that sets the divider ratio for SYSCLK5 can be changed to achieve various clock
frequencies.
• For certain PLL multiplier and PLL post-divider control register (POSTDIV) settings, a higher clock
frequency can be achieved by selecting SYSCLK5 as the clock source for MCLK.
As shown in Figure 6-3, the EMIFB output clock, EMB_CLK, can be sourced from either the output of the
EMIFB LPSC (CLK1 in Figure 6-3) or directly from the output of the clock multiplexer selecting either
DIV4P5 or SYSCLK5 (CLK2 in Figure 6-3). The PINMUX0_15_12 bits in the pin multiplexing control 0
register (PINMUX0) of the SCM control this clock selection.
The purpose in providing two clock sources for EMB_CLK is to support the ability to generate a free
running clock that could be used by an FPGA or for some other purpose. The difference between CLK1
and CLK2 is that if LPSC #6 is configured to clock gate the EMIFB, then CLK1 will also be clock gated,
but CLK2 will not be clock gated. Therefore, if EMIFB is being used to interface to an SDRAM memory, it
is best practice to choose CLK1 as the source for EMB_CLK. This will allow the maximum power savings
when the LPSC is used to clock gate the EMIFB clock. If EMIFB is not in use and the EMB_CLK is used
in the application as a free running clock, then CLK2 should be used as the source for EMB_CLK. This will
allow clock gating of the majority of the logic in EMIFB via the LPSC while still providing a clock on the
EMB_CLK.
NOTE: EMB_CLK is only an output clock. EMIFB does not support an externally provided input
clock.
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