www.ti.com
Clock Management
167
SPRUH91D–March 2013–Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Power Management
9.5 Clock Management
9.5.1 Module Clock ON/OFF
The module clock on/off feature allows software to disable clocks to module individually, in order to reduce
the module's dynamic/switching power consumption down to zero. This device is designed in full static
CMOS; thus, when a module clock stops, the module's state is preserved and retained. When the clock is
restarted, the module resumes operating from the stopping point.
NOTE: Stopping clocks to a module only affects dynamic power consumption, it does not affect
static power consumption of the module or the device.
The power and sleep controller (PSC) module controls module clock gating. If a module's clock(s) is
stopped while being accessed, the access may not occur, and it can potentially result in unexpected
behavior. The PSC provides some protection against such erroneous conditions by monitoring the internal
bus activity to ensure there are no accesses to the module from the internal bus, before allowing module’s
internal clock to be gated. However, it is still recommended that software must ensure that all of the
transactions to the module are finished prior to disabling the clocks.
The procedure to turn module clocks on/off using the PSC is described in the Power and Sleep Controller
(PSC) chapter.
Furthermore, special consideration must be given to DSP clock on/off. The procedure to turn the core
clock on/off is further described in .
Additionally some peripherals implement additional power saving features by automatically shutting of
clock to components within the module , when the logic is not active. This is transparent to you, but
reduces overall dynamic power consumption when modules are not active.
9.5.2 Module Clock Frequency Scaling
Module clock frequency is scalable by programming the PLL multiply and divide parameters. Additionally,
some modules might also have internal clock dividers. Reducing the clock frequency reduces the
dynamic/switching power consumption, which scales linearly with frequency.
The Device Clocking chapter details the clocking structure of the device. The Phase-Locked Loop
Controller (PLLC) chapter describes how to program the PLL0 and PLL1 frequency and the frequency
constraints.
9.5.3 PLL Bypass and Power Down
You can bypass the PLL in the device. Bypassing the PLL sends the PLL reference clock (OSCIN) instead
of the PLL VCO output (PLLOUT) to the system clocks of the PLLC. The PLL OSCIN is typically, at most,
up to 50 MHz. You can use this mode to reduce the core and module clock frequencies to very low
maintenance levels without using the PLL during periods of very low system activity, this again can lower
the overall dynamic/switching power consumption, which is linearly proportional to the frequency.
Furthermore, you can also power-down the PLL when bypassing it to minimize the overall power
consumed by the PLL module.
The Device Clocking chapter and the Phase-Locked Loop Controller (PLLC) chapter describe PLL bypass
and PLL power down.
To Next Page
Loading...
