Texas Instruments TMS320C6745 DSP - EDMA3 CC Error Clear Register (CCERRCLR); EDMA3 CC Error Clear Register (CCERRCLR) Field Descriptions

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SPRUH91D–March 2013–Revised September 2016
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Enhanced Direct Memory Access (EDMA3) Controller
16.4.2.2.6 EDMA3CC Error Clear Register (CCERRCLR)
The EDMA3CC error clear register (CCERRCLR) is used to clear any error bits that are set in the
EDMA3CC error register (CCERR). In addition, CCERRCLR also clears the values of some bit fields in
the queue status registers (QSTATn) associated with a particular event queue. Writing a 1 to any of the
bits clears the corresponding bit in CCERR; writing a 0 has no effect.
The CCERRCLR is shown in Figure 16-53 and described in Table 16-32.
Figure 16-53. EDMA3CC Error Clear Register (CCERRCLR)
31 17 16
Reserved TCCERR
W-0 W-0
15 2 1 0
Reserved QTHRXCD1 QTHRXCD0
W-0 W-0 W-0
LEGEND: W= Write only; -n = value after reset
Table 16-32. EDMA3CC Error Clear Register (CCERRCLR) Field Descriptions
Bit Field Value Description
31-17 Reserved 0 Reserved
16 TCCERR Transfer completion code error clear.
0 No effect.
1 Clears the TCCERR bit in the EDMA3CC error register (CCERR).
15-2 Reserved 0 Reserved
1 QTHRXCD1 Queue threshold error clear for queue 1.
0 No effect.
1 Clears the QTHRXCD1 bit in the EDMA3CC error register (CCERR) and the WM and THRXCD bits in
the queue status register 1 (QSTAT1).
0 QTHRXCD0 Queue threshold error clear for queue 0.
0 No effect.
1 Clears the QTHRXCD0 bit in the EDMA3CC error register (CCERR) and the WM and THRXCD bits in
the queue status register 0 (QSTAT0).