Texas Instruments TMS320C6745 DSP - Multiplexed-Mode Host Write Cycle

UHPI_HCS
HSTRB
UHPI_HRDY
UHPI_HR/W
UHPI_HCNTL[1:0]
UHPI_HHWIL
Data 1 Data 2
UHPI_HD[15:0]
Internal
HPI latches
control information
HPI latches
data
HPI latches
control information
HPI latches
data
www.ti.com Architecture
869
SPRUH91D–March 2013–Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Host Port Interface (HPI)
Figure 21-5. Multiplexed-Mode Host Write Cycle
NOTE: Depending on the type of write operation (HPID without autoincrementing, HPIA, HPIC, or HPID with
autoincrementing) and the state of the FIFO, transitions on UHPI_HRDY may or may not occur. For more information,
see Section 21.2.6.9.