A1 A0 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 C15
ACLKX
AXR
AXEVT
Time slot
N ACLKX cycles (N=number of bits in slot)
AXEVT
Latency
(for Word C)
DSP service time
Setup time
(for Word C)
3 McASP
system clocks +
4 ACLKX cycles
(to write Word C)
5 McASP
system clocks
(A)
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SPRUH91D–March 2013–Revised September 2016
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Multichannel Audio Serial Port (McASP)
24.0.21.3.1 Data Ready Status and Event/Interrupt Generation
24.0.21.3.1.1 Transmit Data Ready
The transmit data ready flag XDATA bit in the XSTAT register reflects the status of the XBUF register. The
XDATA flag is set when data is transferred from the XRBUF[n] buffers to the XRSR[n] shift registers,
indicating that the XBUF is empty and ready to accept new data from the DSP. This flag is cleared when
the XDATA bit is written with a 1, or when all the serializers configured as transmitters are written by the
DSP.
Whenever XDATA is set, an DMA event AXEVT is automatically generated to notify the DMA of the XBUF
empty status. An interrupt AXINT is also generated if XDATA interrupt is enabled in the XINTCTL register
(See Section 24.0.21.5.1 for details).
For DMA requests, the McASP does not require XSTAT to be read between DMA events. This means that
even if XSTAT already has the XDATA flag set to 1 from a previous request, the next transfer triggers
another DMA request.
Since all serializers act in lockstep, only one DMA event is generated to indicate that all active transmit
serializers are ready to be written to with new data.
Figure 24-25 shows the timing details of when AXEVT is generated at the McASP boundary. In this
example, as soon as the last bit (bit A0) of Word A is transmitted, the McASP sets the XDATA flag and
generates an AXEVT event. However, it takes up to 5 McASP system clocks (AXEVT Latency) before
AXEVT is active at the McASP boundary. Upon AXEVT, the DSP can begin servicing the McASP by
writing Word C into the XBUF (DSP Service Time). The DSP must write Word C into the XBUF no later
than the setup time required by the McASP (Setup Time).
The maximum DSP Service Time (Figure 24-25) can be calculated as:
DSP Service Time = Time Slot - AXEVT Latency - Setup Time
Figure 24-25. DSP Service Time Upon Transmit DMA Event (AXEVT)
A This is not the same as AUXCLK. The DSP uses SYSCLK2 as the McASP system clock source.
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