Texas Instruments TMS320C6745 DSP - EMIFA to 8-Bit;16-Bit Memory Interface; Common Asynchronous Interface

EMA_WE_DQM[1:0]
DQ[15:0]
asynchronous
BE[1:0]
EMA_WE
EMA_D[15:0]
EMA_CS[n]
EMIFA
WE
CE
device
16−bit
EMA_D[7:0]
EMA_A[x:0]
EMA_BA[1:0]
DQ[7:0]
A[(x+2):2]
A[1:0]
EMIFA 8−bit
asynchronous
memory
a)EMIFto8-bitmemoryinterface
EMA_D[15:0]
EMA_A[x:0]
EMA_BA[1]
DQ[15:0]
A[(x+1):1]
A[0]
EMIFA 16−bitasynchronous
memory
b)EMIFto16-bitmemoryinterface
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SPRUH91D–March 2013–Revised September 2016
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External Memory Interface A (EMIFA)
Of special note is the connection between the EMIFA and the external device's address bus. The EMIFA
address pin EMA_A[0] always provides the least significant bit of a 32-bit word address. Therefore, when
interfacing to a 16-bit or 8-bit asynchronous device, the EMA_BA[1] and EMA_BA[0] pins provide the
least-significant bits of the halfword or byte address, respectively. Additionally, when the EMIFA interfaces
to a 16-bit asynchronous device, the EMA_BA[0] pin can serve as the upper address line EMA_A[22].
Note that the width of the address bus varies with devices; therefore, see your device-specific data
manual for the EMA_A bus width supported. Figure 18-8 and Figure 18-9 show the mapping between the
EMIFA and the connected device's data and address pins for various programmed data bus widths. The
data bus width may be configured in the asynchronous n configuration register (CEnCFG).
Figure 18-9 shows a common interface between the EMIFA and external asynchronous memory.
Figure 18-9 shows an interface between the EMIFA and an external memory with byte enables. The
EMIFA should be operated in either Normal Mode or Select Strobe Mode when using this interface, so
that the EMA_WE_DQM signals operate as byte enables.
Figure 18-8. EMIFA to 8-bit/16-bit Memory Interface
Figure 18-9. Common Asynchronous Interface