Introduction
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SPRUH91D–March 2013–Revised September 2016
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Host Port Interface (HPI)
21.1 Introduction
The host port interface (HPI) provides a parallel port interface through which an external host processor
can directly access the processor's resources (configuration and program/data memories). The external
host device is asynchronous to the CPU clock and functions as a master to the HPI interface. The HPI
enables a host device and the processor to exchange information via internal or external memory.
Dedicated address (HPIA) and data (HPID) registers within the HPI provide the data path between the
external host interface and the processor resources. An HPI control register (HPIC) is available to the host
and the CPU for various configuration and interrupt functions.
21.1.1 Purpose of the Peripheral
The HPI enables an external host processor (host) to directly access program/data memory on the
processor using a parallel interface. The primary purpose is to provide a mechanism to move data to and
from the processor. In addition to data transfer, the host can also use the HPI to bootload the processor
by downloading program and data information to the processor's memory after power-up.
21.1.2 Features
The HPI supports the following features:
• Multiplexed address/data
• Dual 16-bit halfword cycle access (internal data word is 32-bits wide)
• 16-bit-wide host data bus interface
• Internal data bursting using 8-word read and write first-in, first-out (FIFO) buffers
• HPI control register (HPIC) accessible by both the DSP CPU and the external host
• HPI address register (HPIA) accessible by both the DSP CPU and the external host
• Separate HPI address registers for read (HPIAR) and write (HPIAW) with configurable option for
operating as a single HPI address register
• HPI data register (HPID)/FIFOs providing data-path between external host interface and CPU
resources
• Multiple strobes and control signals to allow flexible host connection
• Asynchronous UHPI_HRDY output to allow the HPI to insert wait states to the host
• Software control of data prefetching to the HPID/FIFOs
• Processor-to-Host interrupt output signal controlled by HPIC accesses
• Host-to-Processor interrupt controlled by HPIC accesses
• Register controlled HPIA and HPIC ownership and FIFO timeout
• Memory-mapped peripheral identification register (PID)
• Bus holders on host data and address buses (these are actually external to HPI module)
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