Texas Instruments TMS320C6745 DSP - MPU Memory Regions; MPU Default Configuration

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SPRUH91D–March 2013–Revised September 2016
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Memory Protection Unit (MPU)
5.1.4 MPU Default Configuration
Two MPUs are supported on the device, one for the 128 kB shared RAM and one for the EMIFB. Table 5-
1 shows the memory regions protected by each MPU. Table 5-2 shows the configuration of each MPU.
(1)
The 128 kB shared RAM is not supported on the C6745 DSP; therefore, the MPU1 is not supported.
Table 5-1. MPU Memory Regions
Unit Memory Protection
Memory Region
Start Address End Address
MPU1 128 kB Shared RAM
(1)
8000 0000h 8001 FFFFh
MPU2 EMIFB C000 0000h DFFF FFFFh
(1)
MPU1 is not supported on the C6745 DSP.
Table 5-2. MPU Default Configuration
Setting MPU1
(1)
MPU2
Default permission Assume allowed Assume allowed
Number of allowed IDs supported 12 12
Number of fixed ranges supported 1 0
Number of programmable ranges supported 6 12
Compare width 1 kB granularity 64 kB granularity
5.2 Architecture
5.2.1 Privilege Levels
The privilege level of a memory access determines what level of permissions the originator of the memory
access might have. Two privilege levels are supported: supervisor and user.
Supervisor level is generally granted access to peripheral registers and the memory protection
configuration. User level is generally confined to the memory spaces that the OS specifically designates
for its use.
DSP CPU instruction and data accesses have a privilege level associated with them. The privilege level is
inherited from the code running on the CPU. See the TMS320C674x DSP CPU and Instruction Set
Reference Guide (SPRUFE8) for more details on privilege levels of the DSP CPU.
Although master peripherals like the EMAC do not execute code, they still have a privilege level
associated with them. Unlike the DSP CPU , the privilege level of this peripheral is fixed.
Table 5-3 shows the privilege ID of the CPU and every mastering peripheral. Table 5-3 also shows the
privilege level (supervisor vs. user) and access type (instruction read vs. data/DMA read or write) of each
master on the device. In some cases, a particular setting depends on software being executed at the time
of the access or the configuration of the master peripheral.