Processor
generator
Clock
DLH:DLL
UART input clock
Input clock
UART
Receiver
timing and
control
Transmitter
timing and
control
Baud
generator
BCLK
Other logic
UART input clock frequency
Divisor
MDR.OSM _ SEL 1
Desired baud rate 13
=
=
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ë û
´
UART input clock frequency
Divisor
MDR.OSM _ SEL 0
Desired baud rate 16
=
=
é ù
ë û
´
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Peripheral Architecture
1263
SPRUH91D–March 2013–Revised September 2016
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Universal Asynchronous Receiver/Transmitter (UART)
29.2 Peripheral Architecture
29.2.1 Clock Generation and Control
The UART bit clock is derived from an input clock to the UART. See your device-specific data manual to
check the maximum data rate supported by the UART.
Figure 29-2 is a conceptual clock generation diagram for the UART. The processor clock generator
receives a signal from an external clock source and produces a UART input clock with a programmed
frequency. The UART contains a programmable baud generator that takes an input clock and divides it by
a divisor in the range between 1 and (2
16
- 1) to produce a baud clock (BCLK). The frequency of BCLK is
sixteen times (16×) the baud rate (each received or transmitted bit lasts 16 BCLK cycles) or thirteen times
(13×) the baud rate (each received or transmitted bit lasts 13 BCLK cycles). When the UART is receiving,
the bit is sampled in the 8th BCLK cycle for 16× over sampling mode and on the 6th BCLK cycle for 13×
over-sampling mode. The 16× or 13× reference clock is selected by configuring the OSM_SEL bit in the
mode definition register (MDR). The formula to calculate the divisor is:
Two 8-bit register fields (DLH and DLL), called divisor latches, hold this 16-bit divisor. DLH holds the most
significant bits of the divisor, and DLL holds the least significant bits of the divisor. For information about
these register fields, see Section 29.3. These divisor latches must be loaded during initialization of the
UART in order to ensure desired operation of the baud generator. Writing to the divisor latches results in
two wait states being inserted during the write access while the baud generator is loaded with the new
value.
Figure 29-3 summarizes the relationship between the transferred data bit, BCLK, and the UART input
clock. Note that the timing relationship depicted in Figure 29-3 shows that each bit lasts for 16 BCLK
cycles . This is in case of 16x over-sampling mode. For 13× over-sampling mode each bit lasts for 13
BCLK cycles .
Example baud rates and divisor values relative to a 150-MHz UART input clock and 16× over-sampling
mode are shown in Table 29-1.
Figure 29-2. UART Clock Generation Diagram
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