Texas Instruments TMS320C6745 DSP - Pixel Clock Frequency Programming Limitations

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SPRUH91D–March 2013–Revised September 2016
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Liquid Crystal Display Controller (LCDC)
The pixel clock frequency is programmed taking into account the limitations shown in Table 23-12.
If CLKDIV equals 0 or 1, the effect is undefined. Dividing the pixel clock frequency by an odd number
distorts the duty cycle.
Table 23-12. Pixel Clock Frequency Programming Limitations
Type of Screen Output (In Bits) Minimum Pixel Clock Divider
TFT 1,2,4,8 BPP 12 ( 1 pixel) 2
TFT 16 BPP 16 (1 pixel) 2
STN monochrome(4 output lines per panel ) 4 (4 pixel) 4
STN monochrome(8 output lines per panel) 8 (8 pixel) 8
STN color 8 (2 2/3 pixel) 3