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Architecture
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SPRUH91D–March 2013–Revised September 2016
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Enhanced Direct Memory Access (EDMA3) Controller
16.2 Architecture
This section discusses the architecture of the EDMA3 controller.
16.2.1 Functional Overview
This section provides an overview of the EDMA3 channel controller (EDMA3CC) and EDMA3 transfer
controller (EDMA3TC).
16.2.1.1 EDMA3 Channel Controller (EDMA3CC)
Figure 16-2 shows a functional block diagram of the EDMA3 channel controller (EDMA3CC).
The main blocks of the EDMA3CC are:
• DMA/QDMA Channel Logic: This block consists of logic that captures external system or peripheral
events that can be used to initiate event triggered transfers, it also includes registers that allow
configuring the DMA/QDMA channels (queue mapping, PaRAM entry mapping). It includes all the
registers for different trigger type (manual, external events, chained and auto triggered) for
enabling/disabling events, and monitor event status.
• Parameter RAM (PaRAM): Maintains parameter set entries for channel and reload parameter sets. The
PaRAM needs to be written with the transfer context for the desired channels and link parameter sets.
• Event queues: These form the interface between the event detection logic and the transfer request
submission logic.
• Transfer Request Submission Logic: This logic processes PaRAM sets based on a trigger event
submitted to the event queue and submits a transfer request (TR) to the transfer controller associated
with the event queue.
• Completion detection: The completion detect block detects completion of transfers by the EDMA3
transfer controller (EDMA3TC) and/or slave peripherals. Completion of transfers can optionally be used
to chain trigger new transfers or to assert interrupts. The logic includes the interrupt processing
registers for enabling/disabling interrupt (to be sent to the CPU), interrupt status/clearing registers.
Additionally there are:
• Region registers: Region registers allow DMA resources (DMA channels and interrupts) to be assigned
to unique regions, which can be owned by unique EDMA programmers (a use model for hetero/multi
core devices) or by unique tasks/threads (a use model for single core devices).
• Debug registers: Debug registers allow debug visibility by providing registers to read the queue status,
channel controller status (what logic within the CC is active), and missed event status.
The EDMA3CC includes two channel types: DMA channels and QDMA channels.
Each channel is associated with a given event queue/transfer controller and with a given PaRAM set. The
main difference between a DMA channel and QDMA channel is how the transfers are triggered by the
system. See Section 16.2.4.
A trigger event is needed to initiate a transfer. For DMA channels, a trigger event may be due to an
external event, manual write to the event set register, or chained event. QDMA channels are autotriggered
when a write is performed to the user-programmed trigger word. All such trigger events are logged into
appropriate registers upon recognition. See DMA channel registers (Section 16.4.2.5) and QDMA channel
registers (Section 16.4.2.7).
Once a trigger event is recognized, the event type/channel is queued in the appropriate EDMA3CC event
queue. The assignment of each DMA/QDMA channel to event queue is programmable. Each queue is
16 deep, so up to 16 events may be queued (on a single queue) in the EDMA3CC at an instant in time.
Additional pending events mapped to a full queue are queued when event queue space becomes
available. See Section 16.2.10.
If events on different channels are detected simultaneously, the events are queued based on fixed priority
arbitration scheme with the DMA channels being higher priority than the QDMA channels. Among the two
groups of channels, the lowest-numbered channel is the highest priority.
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