Texas Instruments TMS320C6745 DSP - Vertical Front Porch (VFP)

LinePulse
(LCD_HSYNC)
HFP =2
VFP =1
VSW=0
VBP =1
HBP =2
Line479Data
LPP =480
Line0Data
PixelClock
(LCD_PCLK)
Data
(LCD_D[x:0])
FramePulse
(LCD_VSYNC)
www.ti.com Registers
971
SPRUH91D–March 2013–Revised September 2016
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Liquid Crystal Display Controller (LCDC)
23.3.10.3 Vertical Front Porch (VFP)
NOTE: Remember that VSW must be programmed to value required minus 1.
The 8-bit vertical front porch (VFP) field is used to specify the number of line clocks to insert at the end of
each frame. Once a complete frame of pixels is transmitted to the LCD display, the value in VFP is used
to count the number of line clock periods to wait. After the count has elapsed the LCD_VSYNC signal is
pulsed in active mode or extra line clocks are inserted as specified by the VSW bit-field in passive mode.
VFP generates from 0–255 line clock cycles (see Figure 23-33).
Figure 23-33. Vertical Front Porch (VFP)