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Registers
819
SPRUH91D–March 2013–Revised September 2016
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External Memory Interface B (EMIFB)
Table 19-34. Performance Counter Filter Configuration
Performance Counter Configuration Register (PCC) Bit
DescriptionCNTRn_CFG CNTRn_REGION_EN CNTRn_MSTID_EN
0 0 0 or 1 Counts the total number of READ/WRITE commands the
external memory controller receives.
The size of counter increments are determines by the size of the
transfer and the default burst size (DBS). The counter breaks up
transfers into sizes according to DBS. Therefore, counter
increments for transfers aligned to DBS are equal to the transfer
size divided by the DBS.
1h 0 0 or 1 Counts the total number of ACTIVATE commands the
external memory controller issues to SDRAM memory.
The counter increments by a value of 1 for every request to
read/write data to a closed bank in SDRAM memory by the
external memory controller.
2h 0 or 1 0 or 1 Counts the total number of READ commands (read accesses)
the EMIFB receives.
Counter increments for transfers aligned to the default burst size
(DBS) are equal to the transfer size divided by the DBS.
3h 0 or 1 0 or 1 Counts the total number of WRITE commands the EMIFB
receives.
Counter increments for transfers aligned to the default burst size
(DBS) are equal to the transfer size of data written to the DDR2
memory controller divided by the DBS.
4h 0 0 Counts the number of external memory controller cycles
(EMB_CLK cycles) that the command FIFO is full.
Use the following to calculate the counter value as a percentage:
% = counter value / total EMB_CLK cycles in a sample period
As the value of this counter approaches 100%, the EMIFB
memory controller is approaching a congestion point where the
command FIFO is full 100% of the time and a command will have
to wait at the SCR to be accepted in the command FIFO.
5h-7h 0 0 Reserved
8h 0 or 1 0 or 1 Counts the number of commands (requests) in the command
FIFO that require a priority elevation.
To avoid command starvation, the EMIFB memory controller can
momentarily raise the priority of the oldest command in the
command FIFO after a set number of transfers have been made.
The PRIO_RAISE bit field in the peripheral bus burst priority
register (BPRIO) sets the number of the transfers that must be
made before the EMIFB memory controller will raise the priority of
the oldest command.
9h 0 0 Counts the number of EMIFB memory controller cycles
(EMB_CLK cycles) that a command is pending in the
command FIFO. This counter increments every cycle the
command FIFO is not empty.
Use the following to calculate the counter value as a percentage:
% = counter value / total EMB_CLK cycles in sample period
As the value of this counter approaches 100%, the number of
cycles the EMIFB has a command in the command FIFO to
service approaches 100%.
Ah-Fh 0 0 Reserved
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