Texas Instruments TMS320C6745 DSP - Configuring CE2 CFG for HY27 UA081 G1 M Example; Configuring NANDFCR for HY27 UA081 G1 M Example

www.ti.com Example Configuration
757
SPRUH91D–March 2013–Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
External Memory Interface A (EMIFA)
Since the value of the W_SETUP/R_SETUP, W_STROBE/R_STROBE, W_HOLD/R_HOLD, and TA fields
are equal to EMIFA clock cycles minus 1 cycle, the CE2CFG should be configured as in Table 18-46. In
this example, although the EMA_WAIT signal is connected to the R/B signal of the NAND Flash the
Extended Wait mode of the EMIFA is not used, therefore the asynchronous wait cycle configuration
register (AWCC) does not need to be programmed.
Table 18-46. Configuring CE2CFG for HY27UA081G1M Example
Parameter Setting
SS Select Strobe mode.
• SS = 0. Places EMIFA in Normal Mode.
EW Extended Wait mode enable.
• EW = 0. Disabled Extended wait mode.
W_SETUP/R_SETUP Read/Write setup widths.
• W_SETUP = 0
• R_SETUP = 2
W_STROBE/R_STROBE Read/Write strobe widths.
• W_STROBE = 6
• R_STROBE = 7
W_HOLD/R_HOLD Read/Write hold widths.
• W_HOLD = 1
• R_HOLD = 0
TA Minimum turnaround time.
• TA = 2
ASIZE Asynchronous device bus width.
• ASIZE = 0, select an 8-bit data bus width.
Since this is a NAND Flash example, the EMIFA must be configured for NAND Flash mode. This is
accomplished by configuring the NAND Flash control register (NANDFCR) as in Table 18-47. In
NANDFCR, chip select space 2 must be configured with NAND Flash mode enabled.
Table 18-47. Configuring NANDFCR for HY27UA081G1M Example
Parameter Setting
CS5ECC NAND Flash ECC start for chip select 5.
• CS5ECC = 0. Not set during configuration. Only set just prior to reading or writing data.
CS4ECC NAND Flash ECC start for chip select 4.
• CS4ECC = 0. Not set during configuration. Only set just prior to reading or writing data.
CS3ECC NAND Flash ECC start for chip select 3.
• CS3ECC = 0. Not set during configuration. Only set just prior to reading or writing data.
CS2ECC NAND Flash ECC start for chip select 2.
• CS2ECC = 0. Not set during configuration. Only set just prior to reading or writing data.
CS5NAND NAND Flash mode for chip select 5.
• CS5NAND = 0. NAND Flash mode is disabled.
CS4NAND NAND Flash mode for chip select 4.
• CS4NAND = 0. NAND Flash mode is disabled.
CS3NAND NAND Flash mode for chip select 3.
• CS3NAND = 0. NAND Flash mode is disabled.
CS2NAND NAND Flash mode for chip select 2.
• CS5NAND = 1. NAND Flash mode is enabled.